AN 855: PCI Express* High Performance Reference Design for Intel® Cyclone® 10 GX

ID 683504
Date 6/08/2018
Public

1.10. Using SignalTap II

Signal Tap II can provide information on the performance of this design. The init signal in the DMA read and write modules transitions to zero at the beginning of the transfer. You can use the init signal as a trigger in the SignalTap II file to capture data.

The tx_st_ready and rx_st_valid are indications of link utilization and throughput. In the transmit direction, the frequent deassertion of the tx_st_ready signal typically indicates that the IP core is not receiving enough credits from the device at the far end of the PCI Express link. It could also indicate that a x4 link has trained to x1. In the receive direction, the deassertion of rx_st_valid indicates that the IP core is not receiving enough data.

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