Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.3.1 Release Notes: Intel FPGA Programmable Acceleration Card N3000-N

ID 683474
Date 6/16/2021
Public

Known Issues

Table 4.  Known Issues in Intel Acceleration Stack v1.3.1 for Intel FPGA PAC N3000-N
Known Issue Details
DDR4 accesses with a burstcount of 64 are not supported.

  • Burstcounts of 1, 2, 4, 8, 16 and 32 are supported.
  • Workaround: None.
  • Status: No planned fix.
Intel provided factory FPGA images may incur packet loss in FPGA when all ports are active and the packet size is not a multiple of 64.

  • The provided FPGA factory images are intended to demonstrate all interfaces. The internal clock rate is not set for dropless packet transfer for all packet sizes. For more details on expected packet drop measurements for the baseline images, refer to Intel Provided FPGA Factory Image Packet Drop.
  • Workaround: While using an aggregated internal packet bus for your Intel® FPGA PAC N3000-N design, set the clock rate to 285 MHz to have no packet drops for all packet sizes. The disaggregated and lightweight packet bus implementation options do not have this issue.
  • Status: No planned fix.
fpgainfo bmc may not return QSFP Supply Voltage if your QSFP module does not support supply voltage and temperature registers.

  • The Intel® MAX® 10 BMC obtains the QSFP module voltage sensor value from the Supply Voltage registers beginning at offset 26, as listed in the Free Side Monitoring Values, Table 6-7, of the SFF-8636 Specification for Management Interface for 4-lane Modules and Cables, rev 2.10a. If the QSA cable is used, it should comply with SFF-8472 standard.
  • Workaround: If your QSFP module does not support this register, please disregard the value returned by the Intel® MAX® 10 BMC when using the fpgainfo bmc command.
  • Status: No planned fix.
The Intel® MAX® 10 BMC drops MCTP packets when SOM bit is 1 and Pkt_seq# is nonzero.

  • The DSP0236 MCTP Base Specification states the that the packet sequence number can be any value 0-3 if the SOM bit is set.
  • Workaround: None.
  • Status: This limitation will be fixed in a future version of the Intel® Acceleration Stack for the Intel FPGA PAC N3000-N.
The PLDM GetPDRRepositoryInfo command reports a constant updateTime field.

  • When the SetSensorThresholds command is issued to update the threshold values, the GetPDRRepositoryInfo updateTime field does not update. Instead the updateTime field always reports July 4th 2018.
  • Workaround: None.
  • Status: No planned fix.
When using the fpgastats command, the Rx Broadcast OK counter (CNTR_RX_BCAST_DATA_OK) increments when oversized packets are received.

  • According to the IEEE 802.3 2018 Specification, only the Rx Oversize Counter (CNTR_RX_OVERSIZE) increments when oversized packets are received.
  • Workaround: None.
  • Status: No planned fix.
Running the fpgastats -B command in a two card system results in inconsistent ordering of MAC wrapper information.

  • When the fpgastats -B <bus> command is issued in a two card system, one card displays MAC wrapper 1 first and the other card displays MAC wrapper 0 first. In either case, the counter information is correct.
  • Workaround: None.
  • Status: This limitation will be fixed in a future version of the Intel® Acceleration Stack for the Intel FPGA PAC N3000-N.
The PCIe link between the Broadcom* PEX8747 PCIe Switch and the Intel Ethernet Controller XL710 downgrades to Gen1 width=0.

  • Include a check for the expected PCIe link speed and width between the PEX8747 PCIe Switch and the downstream Intel XL710. If one of the links reports Width x0, then apply the workaround.
  • Workaround: Issue the rsu bmcimg <bdf> command to power cycle the board.
  • Status: This limitation is fixed in NVM update 8.10, 8.20, 8.30, and 8.40. Newer versions are available on Intel Download Center.
During the server power-down process, PCIe errors may be reported between the PEX8747 PCIe ports and the downstream XL710 Ethernet Controllers. This issue has been observed during AC Power Cycle stress testing.
  • The issue is intermittent with a very low probability of occurring. The issue is only observed during the power-down phase. During the power-up phase, these PCIe errors are not present.
  • After confirming the errors during server power-down, if the PCIe errors cannot be masked, then system should ignore these errors.
  • Workaround: None.
  • Status: No planned fix.

Did you find the information on this page useful?

Characters remaining:

Feedback Message