Migrating your FPGA RTL Design from Intel® Acceleration Stack v1.1 to Intel® Acceleration Stack v1.3.1
- Port your 1.1 FPGA design to work in v1.3.1 RTL. Edit the ccip_std_afu.sv file, change line 52:
localparam int TIMESTAMP_WIDTH = 96
parameter TIMESTAMP_WIDTH = 96
- Recompile your RTL using the make flow as described in the Acceleration Functional Unit Developer Guide.
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