Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.3.1 Release Notes: Intel FPGA Programmable Acceleration Card N3000-N

ID 683474
Date 6/16/2021

Migrating your FPGA RTL Design from Intel® Acceleration Stack v1.1 to Intel® Acceleration Stack v1.3.1

The Intel FPGA PAC N3000-N supports operation at higher temperatures. The v1.3.1 RTL package, provided in the Acceleration Stack for Development, has updated the DDR4 IP core settings to refresh at a faster rate to maintain data integrity at higher temperatures. For your existing 1.1 FPGA design to work in the higher temperature environment supported by Intel FPGA PAC N3000-N, you must perform the following steps:
  1. Port your 1.1 FPGA design to work in v1.3.1 RTL. Edit the file, change line 52:
    localparam int TIMESTAMP_WIDTH             = 96
    parameter TIMESTAMP_WIDTH                  = 96
  2. Recompile your RTL using the make flow as described in the Acceleration Functional Unit Developer Guide.

Did you find the information on this page useful?

Characters remaining:

Feedback Message