PCI Express: Migrating to Stratix 10 from Arria 10 for the Avalon-MM and Avalon-MM DMA Interfaces

ID 683459
Date 1/23/2017

3.8. Hard IP Reconfiguration Interface

Table 9.  Hard IP Reconfiguration Interface
Stratix 10 Arria 10, Stratix V Comments


Not required

Stratix 10: Signal names differ, but the functionality is the same unless otherwise noted below.

Arria 10, Stratix V: A wait request signal is not necessary. Requests always complete in a deterministic number of clock cycles.


Not required

Stratix 10: hip_reconfig_readdatavalid indicates that read data is valid.

Arria 10, Stratix V: a read data valid signal is not necessary. Read data is guaranteed to be valid in the same clock cycle that the read is accepted by the slave interface.







Signal widths changed to correspond to the Stratix 10 transceiver implementation.
Not required ser_shift_load

Stratix 10: ser_shift_load is not required for dynamic reconfiguration on Stratix 10.

Arria 10, Stratix V:

You must toggle ser_shift_load once after changing to user mode before the first access to read-only registers. This signal should remain asserted for a minimum of 324 ns after switching to user mode.
Not required interface_sel

Stratix 10: interface_sel is not required for dynamic reconfiguration on Stratix 10.

Arria 10, Stratix V: interface_sel must be asserted when performing dynamic reconfiguration. Drive interface_sel low for 4 clock cycles after the release of ser_shift_load.