PCI Express: Migrating to Stratix 10 from Arria 10 for the Avalon-MM and Avalon-MM DMA Interfaces

ID 683459
Date 1/23/2017
Public

3.12. PHY Interface for PCI Express (PIPE) Interface

Table 13.  PIPE Interface
Stratix 10 Arria 10, Stratix V Comments

rxeqeval

rxeqinprogress

invalidreq

dirfeedback[5:0] (H-Tile only)

sim_pipe_mask_tx_pll_lock

Not supported

Stratix 10: The PIPE interface is compliant to the PHY Interface for the PCI Express Architecture PCI Express 3.0.

sim_ltssmstate[5:0]

sim_ltssmstate[4:0]

Stratix 10: Provides finer granularity and different encodings. For example, L0 is now 0x11 instead of 0x0F.

Not required

eidleinfersel0[2:0]

Stratix 10: Not required. The PIPE interface is compliant to the Gen3 PIPE specification.

Arria 10, Stratix V: Indicates Electrical Idle entry inference mechanism selection.

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