PCI Express: Migrating to Stratix 10 from Arria 10 for the Avalon-MM and Avalon-MM DMA Interfaces

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ID 683459
Date 1/23/2017
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Configuration Options 3. Interface and Signal Differences A. Document Revision History
3. Interface and Signal Differences x
3.1. Reset Interfaces 3.2. Serial Interface 3.3. Read DMA Interface 3.4. Write DMA Interface 3.5. Avalon-MM Slave Interfaces 3.6. Avalon-MM Master Interfaces 3.7. Control and Status Register Interface 3.8. Hard IP Reconfiguration Interface 3.9. Interrupt Interface 3.10. Error Interface 3.11. Status and Link Training Interface 3.12. PHY Interface for PCI Express (PIPE) Interface 3.13. Test Interface
1. Introduction
2. Configuration Options
3. Interface and Signal Differences
A. Document Revision History

3.12. PHY Interface for PCI Express (PIPE) Interface

Table 13.  PIPE Interface
Stratix 10 Arria 10, Stratix V Comments

rxeqeval

rxeqinprogress

invalidreq

dirfeedback[5:0] (H-Tile only)

sim_pipe_mask_tx_pll_lock

Not supported

Stratix 10: The PIPE interface is compliant to the PHY Interface for the PCI Express Architecture PCI Express 3.0.

sim_ltssmstate[5:0]

sim_ltssmstate[4:0]

Stratix 10: Provides finer granularity and different encodings. For example, L0 is now 0x11 instead of 0x0F.

Not required

eidleinfersel0[2:0]

Stratix 10: Not required. The PIPE interface is compliant to the Gen3 PIPE specification.

Arria 10, Stratix V: Indicates Electrical Idle entry inference mechanism selection.

Level Two Title