PCI Express: Migrating to Stratix 10 from Arria 10 for the Avalon-MM and Avalon-MM DMA Interfaces

ID 683459
Date 1/23/2017
Public

3.7. Control and Status Register Interface

Table 8.  Control and Status Register Interface
Stratix 10 Arria 10, Stratix V Comments

cra_*

Cra*

Signal names differ, but the functionality is the same unless otherwise noted below.

cra_readdatavalid_o

Not required

Stratix 10: cra_readdatavalid_o indicates that read data is valid.

Arria 10, Stratix V: a read data valid signal is not necessary. Read data is guaranteed to be valid in the same clock cycle that the read is accepted by the slave interface.

Did you find the information on this page useful?

Characters remaining:

Feedback Message