PCI Express: Migrating to Stratix 10 from Arria 10 for the Avalon-MM and Avalon-MM DMA Interfaces

ID 683459
Date 1/23/2017

3.7. Control and Status Register Interface

Table 8.  Control and Status Register Interface
Stratix 10 Arria 10, Stratix V Comments



Signal names differ, but the functionality is the same unless otherwise noted below.


Not required

Stratix 10: cra_readdatavalid_o indicates that read data is valid.

Arria 10, Stratix V: a read data valid signal is not necessary. Read data is guaranteed to be valid in the same clock cycle that the read is accepted by the slave interface.

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