4. Using GPIO Intel® FPGA IP in Half-Rate Mode
As shown in Figure 2, in a half-rate mode interface, the A and B signals go through the HR DDIO IN block and output as DATAOUT[0:3]. Transferring data in half-rate mode reduces the core frequency and therefore augments the setup requirement. However, this solution requires design modifications by changing the GPIO Intel® FPGA IP to half-rate mode. The top_w2 design example shows the full implementation of this solution. The outclk0 clock provides 250 MHz as the full-rate frequency and the outclk1 clock provides 125 MHz as the half-rate frequency.
The following figure shows the timing waveform for the FR DDIO IN register to HR DDIO IN registers in the half-rate mode. The launch clock (outclk0) is operating in full-rate mode while the latch clock (outclk1) is operating in half-rate mode. The DDIO IN data is latched at half-cycle of the launch clock at every 2 ns interval.
From the HR DDIO IN registers to the FPGA core registers, the data are latched at half-cycle of the launch clock at every 4 ns interval as shown in the following figure.
This design provides a setup slack of 1.617 ns from HR DDIO IN registers to the FPGA core registers. However, this solution utilizes more resources to implement half-rate data transfer in the design.
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