When using the top I/O sub-bank for GPIO applications, you may see timing violations on the half-cycle transfer from the input data pins to the FPGA core due to the long data path. The pins in the top I/O sub-banks are identified as pin index 48 to 95 in the device pin-out files.
This application note describes two methods to resolve these timing violations using the GPIO Intel® FPGA IP. The analysis in this document focuses on the input data paths from the GPIO Intel® FPGA IP to the FPGA core. Follow the general best practices for timing closure in FPGA designs to resolve timing violations for other data paths.
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