AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel® Agilex™ Devices

ID 683457
Date 12/20/2022
Public

1. Overview

Intel® Agilex™ devices have general-purpose I/O banks located at the top and bottom of the device. Each I/O bank has two sub-banks. The top I/O sub-bank is located near to the edge of the die while the bottom sub-bank is located near to the FPGA core. In each sub-bank, there is a dedicated I/O PLL and four I/O lanes with 12 I/O pins in each lane for you to design your general-purpose I/O (GPIO) applications.
Figure 1.  Intel® Agilex™ I/O Bank Structure (Top View)This figure shows the I/O bank structure of Intel® Agilex™ AGF 014 device. Different device packages have different number of I/O banks. Refer to the device pin-out files for available I/O banks for each device package.

When using the top I/O sub-bank for GPIO applications, you may see timing violations on the half-cycle transfer from the input data pins to the FPGA core due to the long data path. The pins in the top I/O sub-banks are identified as pin index 48 to 95 in the device pin-out files.

This application note describes two methods to resolve these timing violations using the GPIO Intel® FPGA IP. The analysis in this document focuses on the input data paths from the GPIO Intel® FPGA IP to the FPGA core. Follow the general best practices for timing closure in FPGA designs to resolve timing violations for other data paths.

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