AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel Agilex® 7 F-Series and I-Series Devices

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ID 683457
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Design Examples Requirements 3. Using A Falling Edge Clock for Data Capturing in Full-rate Transfer Mode 4. Using GPIO Intel® FPGA IP in Half-Rate Mode 5. Solutions Comparison 6. Document Revision History for AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel Agilex® 7 F-Series and I-Series Devices
1. Overview x
1.1. GPIO Intel® FPGA IP Architecture 1.2. Input Data Path Timing Violations
3. Using A Falling Edge Clock for Data Capturing in Full-rate Transfer Mode x
3.14.1. Design Example Walkthrough3.14.1. Design Example Walkthrough
4. Using GPIO Intel® FPGA IP in Half-Rate Mode x
3.14.1. Design Example Walkthrough3.14.1. Design Example Walkthrough
1. Overview
2. Design Examples Requirements
3. Using A Falling Edge Clock for Data Capturing in Full-rate Transfer Mode
4. Using GPIO Intel® FPGA IP in Half-Rate Mode
5. Solutions Comparison
6. Document Revision History for AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel Agilex® 7 F-Series and I-Series Devices

5. Solutions Comparison

Table 1.  Solutions ComparisonThis table lists the comparison between the two solutions.
Solution Setup Relationship Setup Slack Timing Path Advantages
From To
Falling edge clock data capturing

Full cycle latch

(4 ns)

1.814 ns

DDIO IN pin FPGA core register
  • Full rate transfer with maximum operating frequency
  • Larger setup slack
  • No additional latency
Half-rate transfer mode

Half cycle latch

(2 ns)

1.582 ns

FR DDIO IN pin HR DDIO IN registers in GPIO Intel® FPGA IP
  • Adequate setup slack
  • Larger hold slack (4.820 ns)

Half cycle latch

(4 ns)

1.617 ns

HR DDIO IN registers in GPIO Intel® FPGA IP FPGA core register
Level Two Title