AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel® Agilex™ Devices

ID 683457
Date 12/21/2020
Public

5. Solutions Comparison

Table 1.  Solutions ComparisonThis table lists the comparison between the two solutions.
Solution Setup Relationship Setup Slack Timing Path Advantages
From To
Falling edge clock data capturing

Full cycle latch

(4 ns)

1.814 ns

DDIO IN pin FPGA core register
  • Full rate transfer with maximum operating frequency
  • Larger setup slack
  • No additional latency
Half-rate transfer mode

Half cycle latch

(2 ns)

1.582 ns

FR DDIO IN pin HR DDIO IN registers in GPIO Intel® FPGA IP
  • Adequate setup slack
  • Larger hold slack (4.820 ns)

Half cycle latch

(4 ns)

1.617 ns

HR DDIO IN registers in GPIO Intel® FPGA IP FPGA core register

Did you find the information on this page useful?

Characters remaining:

Feedback Message