AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel® Agilex™ Devices

ID 683457
Date 12/21/2020
Public

3. Using A Falling Edge Clock for Data Capturing in Full-rate Transfer Mode

As shown in Figure 2, the full-rate transfer mode is represented by signals A and B. In the full-rate mode interface, the two signals bypass the half-rate block. The timing violation on half-cycle transfer from the GPIO Intel® FPGA IP to FPGA core is due to a tighter setup requirement. To rectify this, use a falling edge clock to capture the data because the full cycle window provides a larger setup requirement to fulfill the timing as shown in the top_w1 design example.

Figure 5. Block Diagram of Falling Edge Clock Core Register

The following figure shows the timing waveform of the design example using a falling edge clock. The latch clock now has a full cycle window of 4 ns to capture the input data.

Figure 6. Timing Waveform for Setup Time Using Falling Edge Clock

This solution provides a setup slack of 1.814 ns with no additional latency to the design.

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