1.1. GPIO Intel® FPGA IP Architecture
The GPIO Intel® FPGA IP comprises of three components:
- Double data rate input/output (DDIO)—halves or doubles the data-rate of a communication channel.
- Delay chains—configure the delay chains to perform specific delay and assist in I/O timing closure.
- I/O buffers—connect the pads to the FPGA.
The GPIO Intel® FPGA IP has Double Data Rate I/O (DDIO) blocks in the input path (DDIO IN) and DDIO blocks in the output path (DDIO OUT). Each path consists of one full-rate DDIO block (FR DDIO IN) and two half-rate DDIO blocks (HR DDIO IN). The subsequent content in this document focuses only on the input data path of the GPIO Intel® FPGA IP.
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