AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel® Agilex™ Devices

ID 683457
Date 12/21/2020
Public

1.1. GPIO Intel® FPGA IP Architecture

The GPIO Intel® FPGA IP comprises of three components:

  • Double data rate input/output (DDIO)—halves or doubles the data-rate of a communication channel.
  • Delay chains—configure the delay chains to perform specific delay and assist in I/O timing closure.
  • I/O buffers—connect the pads to the FPGA.

The GPIO Intel® FPGA IP has Double Data Rate I/O (DDIO) blocks in the input path (DDIO IN) and DDIO blocks in the output path (DDIO OUT). Each path consists of one full-rate DDIO block (FR DDIO IN) and two half-rate DDIO blocks (HR DDIO IN). The subsequent content in this document focuses only on the input data path of the GPIO Intel® FPGA IP.

The following figure shows the input data path of the GPIO Intel® FPGA IP. The pad receives the data and the FR DDIO IN (1) block captures data on the rising and falling edges of the CLK_FR clock. The data is sent through signals (A) and (B) to the HR DDIO IN blocks. HR DDIO IN (2) and HR DDIO IN (3) blocks halve the data rate and presents the data through DATAOUT[3:0].
Figure 2. Timing Components of a Simplified GPIO Input Path

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