AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel Agilex® 7 F-Series and I-Series Devices

ID 683457
Date 10/02/2023

2. Design Examples Requirements

Software Requirements

There are three design example revisions described in this document:
  • top—original design example with setup timing violation.
  • top_w1—design example using falling edge clock latching solution.
  • top_w2—design example using half-rate transfer mode solution.

All three design examples were created using the Intel Agilex® 7 F-Series AGFA014R243E3V device in the Intel® Quartus® Prime Pro Edition software version 23.3.