AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel® Agilex™ Devices

ID 683457
Date 12/21/2020
Public

2. Design Examples Requirements

Software Requirements

There are three design example revisions described in this document:
  • top—original design example with setup timing violation.
  • top_w1—design example using falling edge clock latching solution.
  • top_w2—design example using half-rate transfer mode solution.

All three design examples were created using the Intel® Agilex™ AGFA014R243E3V device in the Intel® Quartus® Prime Pro Edition software version 20.3.

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