AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel Agilex® 7 F-Series and I-Series Devices

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ID 683457
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Design Examples Requirements 3. Using A Falling Edge Clock for Data Capturing in Full-rate Transfer Mode 4. Using GPIO Intel® FPGA IP in Half-Rate Mode 5. Solutions Comparison 6. Document Revision History for AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel Agilex® 7 F-Series and I-Series Devices
1. Overview x
1.1. GPIO Intel® FPGA IP Architecture 1.2. Input Data Path Timing Violations
3. Using A Falling Edge Clock for Data Capturing in Full-rate Transfer Mode x
3.14.1. Design Example Walkthrough3.14.1. Design Example Walkthrough
4. Using GPIO Intel® FPGA IP in Half-Rate Mode x
3.14.1. Design Example Walkthrough3.14.1. Design Example Walkthrough
1. Overview
2. Design Examples Requirements
3. Using A Falling Edge Clock for Data Capturing in Full-rate Transfer Mode
4. Using GPIO Intel® FPGA IP in Half-Rate Mode
5. Solutions Comparison
6. Document Revision History for AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel Agilex® 7 F-Series and I-Series Devices

6. Document Revision History for AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel Agilex® 7 F-Series and I-Series Devices

Document Version Changes
2023.10.02 Updated design example support for Intel® Quartus® Prime Pro Edition software version 23.3.
2023.04.10 Updated design example support for Intel® Quartus® Prime Pro Edition software version 23.1.
2023.03.12
  • Updated product family name to " Intel Agilex® 7".
  • Updated content to clarify that the information applies only to F-Series and I-Series FPGAs.
  • Updated links to the design example files.
  • Updated links to the Intel Agilex® 7 General-Purpose I/O User Guide: F-Series and I-Series.
  • Retitled the document from AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel® Agilex™ Devices to AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel Agilex® 7 F-Series and I-Series Devices
2022.12.20
  • Updated Design Example Walkthrough under Using A Falling Edge Clock for Data Capturing in Full-rate Transfer Mode.
  • Updated Design Example Walkthrough under Using GPIO in Half-Rate Mode.
2020.12.21 Initial release.
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