Power and Thermal Calculator User Guide

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ID 683445
Date 5/08/2025
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Overview of the Power and Thermal Calculator 2. Estimating Power Consumption with the Power and Thermal Calculator 3. Power and Thermal Calculator Graphical User Interface 4. Power and Thermal Calculator Pages 5. Factors Affecting the Accuracy of the PTC 6. Power and Thermal Calculator User Guide Archive 7. Document Revision History for the Power and Thermal Calculator User Guide A. Measuring Static Power
1. Overview of the Power and Thermal Calculator x
1.1. Accessing the Power and Thermal Calculators 1.2. PTC Power Model Status 1.3. Definitions of Power Terms Used in this Document
2. Estimating Power Consumption with the Power and Thermal Calculator x
2.1. Estimating Power Before Starting the FPGA Design 2.2. Estimating Power While Creating the FPGA Design 2.3. Estimating Power After Completing the FPGA Design 2.4. Estimating Power for Dual-Core Devices
2.2. Estimating Power While Creating the FPGA Design x
2.2.1. Importing a .qptc File Generated in the Quartus® Prime Power Analyzer
3. Power and Thermal Calculator Graphical User Interface x
3.1. PTC Select Family Dialog Box 3.2. PTC Primary GUI Components 3.3. PTC - IP Wizard 3.4. PTC Searchable Drop-Down Lists 3.5. Deleting Rows from Data Entry Pages 3.6. Finding Resources Using the Find Dialog Box
3.2. PTC Primary GUI Components x
3.2.1. PTC Data Entry Pages 3.2.2. PTC Design Hierarchy 3.2.3. PTC IP Power Summary 3.2.4. PTC Field Types 3.2.5. PTC Data Entry Error Messages
3.2.2. PTC Design Hierarchy x
3.2.2.1. Using Design Hierarchies in the Power and Thermal Calculator (PTC) 3.2.2.2. Entering Hierarchy Information Into the PTC 3.2.2.3. Exporting, Importing, Duplicating, Renaming, and Deleting Hierarchies in the PTC 3.2.2.4. Bulk Editing Hierarchies in the PTC
3.2.4. PTC Field Types x
3.2.4.1. PTC Input Field Dependencies
4. Power and Thermal Calculator Pages x
4.1. PTC - Power Summary/Navigation 4.2. PTC - Common Page Elements 4.3. PTC - Main Page 4.4. PTC - Logic Page 4.5. PTC - RAM Page 4.6. PTC - DSP Page 4.7. PTC - Clock Page 4.8. PTC - PLL Page 4.9. PTC - I/O Page 4.10. PTC - Transceiver Page 4.11. PTC - HPS Page 4.12. PTC - Crypto Page 4.13. PTC - NOC Page 4.14. PTC - HBM Page 4.15. PTC - Thermal Page 4.16. PTC - Report Page
4.3. PTC - Main Page x
4.3.1. PTC - Device Selection and Thermal Analysis Windows
4.10. PTC - Transceiver Page x
4.10.1. Estimating E-Tile Channel PLL Power with the Power and Thermal Calculator
5. Factors Affecting the Accuracy of the PTC x
5.1. Toggle Rate 5.2. I/O Bank Allocation
Answers to Top FAQs
1. Overview of the Power and Thermal Calculator
2. Estimating Power Consumption with the Power and Thermal Calculator
3. Power and Thermal Calculator Graphical User Interface
4. Power and Thermal Calculator Pages
5. Factors Affecting the Accuracy of the PTC
6. Power and Thermal Calculator User Guide Archive
7. Document Revision History for the Power and Thermal Calculator User Guide
A. Measuring Static Power

4.14. PTC - HBM Page

The HBM data entry page of the Power and Thermal Calculator (PTC) shows the power information pertaining to high-bandwidth memory (HBM). This page is available for Agilex™ 7 M-series and Stratix® 10 devices only.
Table 29.  HBM Channel Configuration
Column Heading   Description
Entity Name   A user-editable field to name each entity of the design.
Full Hierarchy Name   Specify the hierarchical path relevant to this entry. This is an optional entry. When entering levels of hierarchy, the pipe character (|) denotes a level of hierarchy.
HBM ID   Select the top or bottom HBM stack in devices that include multiple stacks.
Channel ID   Selects a particular die in the stack.
PC0 Traffic Pattern   Select the traffic pattern that most closely matches your application. (PC0 and PC1 refer to the two pseudo-channels that each physical channel [0-7] is divided into; you can select different traffic patterns for each pseudo-channel.) Intel Stratix 10 devices only.
PC1 Traffic Pattern   Select the traffic pattern that most closely matches your application. (PC0 and PC1 refer to the two pseudo-channels that each physical channel [0-7] is divided into; you can select different traffic patterns for each pseudo-channel.) Intel Stratix 10 devices only.
Pseudo channel 0 Read Rate % Select to most closely match your application. Agilex™ 7 M-series devices only.
Bandwidth %
Page Hit Rate %
Pseudo channel 1 Read Rate % Select to most closely match your application. Agilex™ 7 M-series devices only.
Bandwidth %
Page Hit Rate %
User Comment   User Comment field.
Figure 52. HBM Page of the PTC ( Stratix® 10 Devices)


Figure 53. HBM Page of the PTC ( Agilex™ 7 M-series Devices)


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