Power and Thermal Calculator User Guide

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ID 683445
Date 5/08/2025
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Ixiasoft

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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Overview of the Power and Thermal Calculator 2. Estimating Power Consumption with the Power and Thermal Calculator 3. Power and Thermal Calculator Graphical User Interface 4. Power and Thermal Calculator Pages 5. Factors Affecting the Accuracy of the PTC 6. Power and Thermal Calculator User Guide Archive 7. Document Revision History for the Power and Thermal Calculator User Guide A. Measuring Static Power
1. Overview of the Power and Thermal Calculator x
1.1. Accessing the Power and Thermal Calculators 1.2. PTC Power Model Status 1.3. Definitions of Power Terms Used in this Document
2. Estimating Power Consumption with the Power and Thermal Calculator x
2.1. Estimating Power Before Starting the FPGA Design 2.2. Estimating Power While Creating the FPGA Design 2.3. Estimating Power After Completing the FPGA Design 2.4. Estimating Power for Dual-Core Devices
2.2. Estimating Power While Creating the FPGA Design x
2.2.1. Importing a .qptc File Generated in the Quartus® Prime Power Analyzer
3. Power and Thermal Calculator Graphical User Interface x
3.1. PTC Select Family Dialog Box 3.2. PTC Primary GUI Components 3.3. PTC - IP Wizard 3.4. PTC Searchable Drop-Down Lists 3.5. Deleting Rows from Data Entry Pages 3.6. Finding Resources Using the Find Dialog Box
3.2. PTC Primary GUI Components x
3.2.1. PTC Data Entry Pages 3.2.2. PTC Design Hierarchy 3.2.3. PTC IP Power Summary 3.2.4. PTC Field Types 3.2.5. PTC Data Entry Error Messages
3.2.2. PTC Design Hierarchy x
3.2.2.1. Using Design Hierarchies in the Power and Thermal Calculator (PTC) 3.2.2.2. Entering Hierarchy Information Into the PTC 3.2.2.3. Exporting, Importing, Duplicating, Renaming, and Deleting Hierarchies in the PTC 3.2.2.4. Bulk Editing Hierarchies in the PTC
3.2.4. PTC Field Types x
3.2.4.1. PTC Input Field Dependencies
4. Power and Thermal Calculator Pages x
4.1. PTC - Power Summary/Navigation 4.2. PTC - Common Page Elements 4.3. PTC - Main Page 4.4. PTC - Logic Page 4.5. PTC - RAM Page 4.6. PTC - DSP Page 4.7. PTC - Clock Page 4.8. PTC - PLL Page 4.9. PTC - I/O Page 4.10. PTC - Transceiver Page 4.11. PTC - HPS Page 4.12. PTC - Crypto Page 4.13. PTC - NOC Page 4.14. PTC - HBM Page 4.15. PTC - Thermal Page 4.16. PTC - Report Page
4.3. PTC - Main Page x
4.3.1. PTC - Device Selection and Thermal Analysis Windows
4.10. PTC - Transceiver Page x
4.10.1. Estimating E-Tile Channel PLL Power with the Power and Thermal Calculator
5. Factors Affecting the Accuracy of the PTC x
5.1. Toggle Rate 5.2. I/O Bank Allocation
Answers to Top FAQs
1. Overview of the Power and Thermal Calculator
2. Estimating Power Consumption with the Power and Thermal Calculator
3. Power and Thermal Calculator Graphical User Interface
4. Power and Thermal Calculator Pages
5. Factors Affecting the Accuracy of the PTC
6. Power and Thermal Calculator User Guide Archive
7. Document Revision History for the Power and Thermal Calculator User Guide
A. Measuring Static Power

4.10.1. Estimating E-Tile Channel PLL Power with the Power and Thermal Calculator

You can estimate E-tile channel PLL power for Stratix® 10 devices, by adding a Transmitter-only row to the Transceiver page of the Power and Thermal Calculator (PTC).

The following three examples illustrate the PTC configuration for various E-tile channel PLL requirements.

Table 23.  E-Tile Channel PLL configured for: Reference clock = 200MHz, pll_clkout1 = 800MHz, pll_clkout2 = 400MHz
Operation Mode Data Rate Digital/Analog Width Power Mode FEC EHIP Modulation Digital Freq # Refclks Refclk Freq VOD
Transmitter Only 12800 16 Normal Power Bypass Bypass NRZ 0 1 200 0
Table 24.  E-Tile Channel PLL configured for: Reference clock = 125MHz, pll_clkout1 = 500MHz, pll_clkout2 = 250MHz
Operation Mode Data Rate Digital/Analog Width Power Mode FEC EHIP Modulation Digital Freq # Refclks Refclk Freq VOD
Transmitter Only 8000 16 Normal Power Bypass Bypass NRZ 0 1 125 0
Table 25.  E-Tile Channel PLL configured for: Reference clock = 307MHz, pll_clkout1 = 491MHz, pll_clkout2 = 245MHz
Operation Mode Data Rate Digital/Analog Width Power Mode FEC EHIP Modulation Digital Freq # Refclks Refclk Freq VOD
Transmitter Only 19660.8 40 Normal Power Bypass Bypass NRZ 0 1 307 0

Alternatively, you can instantiate an E-Tile Transceiver-native PHY IP in PLL mode in your Quartus® Prime project, compile the project, and view the configuration in the PTC.

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