4.15. Intel® FPGA PTC - Thermal Page
Thermal Page for Agilex™ FPGA Portfolio Devices
On the Main worksheet, verify that Power Characteristics is set to Maximum, and then select the desired Calculation mode from the drop-down menu on the Main or Thermal page.
![](/content/dam/docs/us/en/683445/24-1/mfd1612900792571.png)
In the above figure, input parameters are circled in blue and reporting fields are circled in red.
Parameter | Description |
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Calculation Mode | Specifies the calculation mode for the thermal solver to use. The available choices are:
Note: To enable selection of non-constant calculation modes, the Power characteristics field in the Device selection group box of the Main page must be set to Maximum.
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Apply Additional Margin | Specifies, as a percentage, the amount of additional margin to apply to detailed thermal analysis results. The default value is 0%. Valid values are 0-25%. The recommended margin for Agilex™ 5 and Agilex™ 7 devices is 10%. Consult your Intel Field Application Engineer (FAE) if you require additional guidance on margin power.
Note:
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TSD Mode | Indicates the method by which sensor temperatures are reported. This parameter has no effect on maximum junction temperature or temperature margin. |
Junction temperature, TJ (°C) | Allows you to specify the junction temperature for all dies in the package. This field is available only when the selected Calculation mode is Use a constant junction temperature. |
Ambient Temp, TA (°C) | Allows you to specify the temperature of the air that is cooling the device. |
Max. Junction Temp, TJ-MAX (°C) | Allows you to specify the maximum junction temperature that no part of any die in the package should exceed. |
Cooling Solution ΨCA(°C/W) | Allows you to specify the cooling solution when you have selected the Use a constant junction temperature, Find available thermal margin for cooling solution, or Find ambient temperature for specified cooling solution calculation mode. |
Column Heading | Description |
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Max. ΨJC(°C/W) | ψJC is the thermal resistance between each of the dies in the package and the center of the package integrated heat spreader. This field shows the maximum ΨJC among all dies, assuming the recommended ΨCA value below. |
Recommended ambient Temperature TA(°C) | TA is the recommended ambient temperature for the recommended cooling solution. |
Recommended cooling solution ΨCA(°C/W) | ψCA is the thermal resistance between the center of the package integrated heat spreader (IHS) and ambient temperature. The recommended ΨCA is the highest possible thermal resistance of the cooling solution that ensures no part of any die exceeds the specified maximum junction temperature. |
Total Power (W) | The total power consumption. |
Column Heading | Description | ||
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Die | The die for which margin is reported:
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Power (W) | The thermal power dissipated by the specified die. This is the power used in the thermal analysis.
Note: The power listed on the Thermal page is currently pessimistic; the overall total power reported does not match the total on-chip power dissipation on the Power Summary page.
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Margin | Temperature (Δ°C) | The calculated temperature margin in °C for the specified die, relative to the maximum TJ. | |
Power (ΔW) | The amount of power in watts that can be added to the specified die, before reaching its maximum TJ. |
Temperature margins are calculated relative to a designated maximum junction temperature, TJ. It is possible that one or more dies may have zero temperature margin, because the solution is calculated for that maximum TJ. The calculated power margins indicate the power buffer available before the maximum TJ is exceeded, assuming the same cooling conditions. The calculated power value provides only an approximate estimate of power that can be added to the specific die before reaching its maximum TJ. The actual margin depends on the specific subsystem to which the power is added. Note that any increase or decrease in power changes the required cooling solution.
Column Heading | Description | |
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Monitor | Location | The die for which the temperature is reported:
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Sensor | The digital thermal sensor (DTS) or thermal diode (TD) sensor reporting the temperature. | |
Temperature Target (°C) | The calculated temperature for the target location and sensor, when the system is operating. |
The monitor sensors report FPGA temperatures at the specified locations when the system is operating. These sensors may not necessarily be at the hottest locations on the die, and therefore can report values that are lower than the actual maximums in the design.
Thermal Page for Stratix® 10 Devices
![](/content/dam/docs/us/en/683445/24-1/hzt1583606452236.png)
In the above figure, input parameters are circled in blue and reporting fields are circled in red.
Parameter Name | Description |
---|---|
Calculation Mode | Specifies the calculation mode for the thermal solver to use.
Note: To enable selection of non-constant calculation modes, the Power characteristics field in the Device selection group box of the Main page must be set to Maximum.
|
Apply Additional Margin | Specifies as a percentage, the amount of additional margin to apply to detailed thermal analysis results. The default value is 0%. Valid values are 0–25%. The recommended margin for Stratix® 10 devices is 25%. Consult your Intel Field Application Engineer (FAE) if you require additional guidance on margin power.
Note:
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TSD Mode | Specify the method by which offset temperatures are provided—such as from a thermal diode, or a digital temperature sensing mechanism. |
Junction temperature, TJ (°C) | Specify the junction temperature for all dies in the package. This field applies only when the selected Calculation mode value is Use a constant junction temperature. |
Ambient Temp, TA (°C) | Specify the temperature of the air that is cooling the device. |
Max. Junction Temp, TJ-MAX (°C) | Specify the maximum junction temperature that no part of any die in the package should exceed. |
Cooling Solution ΨCA(°C/W) | ψCA is the thermal resistance between the center of the package integrated heat spreader (IHS) and ambient temperature. The recommended ΨCA is the highest possible thermal resistance of the cooling solution that ensures no part of any die exceeds the specified maximum junction temperature. |
Max. ΨJC(°C/W) | ψJC is the thermal resistance between each of the dies in the package and the center of the package integrated heat spreader. This field shows the maximum ΨJC among all dies, assuming the recommended ΨCA value above. |
Row Name | Description |
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Max. Junction | The maximum junction temperature that no part of any die in the package should exceed. |
FPGA Core Junction | The maximum junction temperature that no part of any die in the package should exceed. |
Case | The case temperature, which is the temperature at the top center of the integrated heat spreader, assuming the recommended ΨCA value listed above. |
Ambient | The temperature of the air that is cooling the device. |
Row Name | Description | |
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Total | Provides total power consumption of all dies in the package. | |
FPGA Core | The total thermal power consumption of the main FPGA die containing core logic, assuming the recommended ΨCA value. This power is reported at the actual temperature of the core die, assuming the recommended ΨCA value. This temperature may be equal to the maximum junction temperature if the FPGA core die is at the highest temperature among all dies (also known as a hot spot). The FPGA core may also be at a lower temperature, if the hot spot is elsewhere in the package (i.e. on another die). | |
Transceiver | HSSI_0_0 | The total power consumption of HSSI_0_0, assuming the recommended ΨCA value. This power is reported at the actual temperature of the specific die, assuming the recommended ΨCA value above. This temperature may be equal to the maximum junction temperature if a specific die is the hot spot, or it may be at a lower temperature if the hot spot is elsewhere in the package.
Note: Each transceiver die in the package reports a small amount of static power even when no channels are used in the corresponding transceiver tile and transceiver rails (VCCR_GXB, VCCT_GXB, and VCCH_GXB) of that tile are grounded. This is an expected result.
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HSSI_1_0 | ||
HSSI_2_0 | ||
HSSI_0_1 | ||
HSSI_1_1 | ||
HSSI_2_1 | ||
HBM | Top | The total thermal power consumption of HBM TOP or HBM BOT, assuming the recommended ΨCA value. This power is reported at the actual temperature of the specific die, assuming the recommended ΨCA value above. This temperature may be equal to the maximum junction temperature if a specific die is the hot spot, or it may be at a lower temperature if the hot spot is elsewhere in the package. |
Bot |
Row Name | Description |
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Recommended ψCA (°C/W) | The thermal resistance between the center of the package integrated heat spreader and the ambient temperature, assuming the specific core temperature in the given table row. For each row, this is the ΨCA value that would cause the FPGA core junction temperature to be at the specific value for a given row. |
Row Name | Description | |
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FPGA Core | The thermal resistance between the main FPGA core die and the center of the package integrated heat spreader, assuming the recommended ΨCA value. | |
Transceiver | HSSI_0_0 | The thermal resistance between HSSI_0_0 and the center of the package integrated heat spreader, assuming the recommended ΨCA value. |
HSSI_1_0 | ||
HSSI_2_0 | ||
HSSI_0_1 | ||
HSSI_1_1 | ||
HSSI_2_1 | ||
HBM | TOP | The thermal resistance between HBM TOP or HBM BOT and the center of the package integrated heat spreader, assuming the recommended ΨCA value. |
BOT |
Row Name | Description | |
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FPGA Core | The temperature difference between the hot spot on the main FPGA core and location of the thermal sensing diode (TSD) with the highest temperature reported using the Intel Temperature IP Sense software. (When the IP sense method is used to read the TSDs, all the TSD locations are read and the highest of these is reported.) | |
Transceiver | HSSI_0_0 | The temperature difference between the hot spot on the corresponding transceiver die and location of the thermal sensing diode (TSD) with the highest temperature reported using the Intel Temperature IP Sense software. (When the IP sense method is used to read the TSDs, all the TSD locations are read and the highest of these is reported.) FPGA transceiver temperature = FPGA transceiver TSD temperature measured using the IP sense method + Transceiver TSD offset. (If you are not using the Intel Temperature IP Sense software to read the TSD offsets, contact your Intel support representative for a workaround to get the correct TSD temperature.) |
HSSI_1_0 | ||
HSSI_2_0 | ||
HSSI_0_1 | ||
HSSI_1_1 | ||
HSSI_2_1 |
For more information about HSSI_x_y locations, refer to the Physical Package Structure topic in AN 787: Stratix® 10 Thermal Modeling and Management.
Tables above show variations of thermal parameters and power consumption with changing junction temperature of the main FPGA core die. Three values are provided for each parameter. The Design Max column contains FPGA core temperature and other parameters assuming the recommended ΨCA value above. The -5°C column provides values of all parameters when FPGA core temperature is 5°C lower than in the Design Max column. Similarly, the +5°C column provides values of all parameters when FPGA core temperature is 5°C higher than in the Design Max column. It is important to realize that under the conditions in the +5°C column at least one part of one die in the package exceeds the requested maximum junction temperature, and may even exceed the maximum allowed value for the device. Therefore the values in the +5°C column should be used only as an estimate of power dependence on temperature for the purpose of computational fluid dynamic (CFD) simulation, and not for any other purpose
In extreme cases, such as thermal runaway, it may not be possible to calculate the values for +/- 5 degrees, in which case the Thermal worksheet displays the error message: ERROR: Could not calculate parameter variation with core temperature. Try adjusting TJ-MAX to obtain temperature-dependent parameters. When this error occurs, the recommended ΨCA value and all other values above are valid, but the table showing variation of thermal parameters and power consumption with changing junction temperature of the main FPGA core die contains some invalid values. As the error text indicates, adjusting the maximum junction temperature may allow the thermal solver to calculate this dependence, albeit at a different range of FPGA core temperatures than the usual range.