Intel® FPGA Power and Thermal Calculator User Guide

ID 683445
Date 4/01/2024
Document Table of Contents

4.7. Intel® FPGA PTC - Clock Page

Each row in the Clock page of the Intel® FPGA Power and Thermal Calculator (PTC) represents a clock network or a separate clock domain in the design.

Agilex™ 5, Agilex™ 7, and Stratix® 10 devices support global, regional, and periphery clock networks. The Intel® FPGA PTC does not distinguish between global or regional clocks because the difference in power is not significant.

Figure 40. Clock Page of the Intel® FPGA PTC

Table 15.  Clock Page Information
Column Heading Description
Entity Name Enter a name for the clock entity in this column. This is an optional value.
Full Hierarchy Name Enter the full hierarchy name for the entity represented in this row. Delimit levels of hierarchy with a vertical bar ( | ) symbol, for example: a|b|c.
Clock Freq (MHz) Enter the frequency of the clock domain. This value is limited by the maximum frequency specification for the device family.

When you import a design from the Quartus® Prime software, some imported clocks may have a frequency of 0 MHz, due to either of the following reasons:

  • The Quartus® Prime software did not have sufficient information to determine clock frequency due to incomplete clock constraints.
  • Clock resources were used to route a reset signal, which toggles infrequently, so its frequency is reported as 0 MHz.
Total Fanout

Enter the total number of flipflops, hyper-registers, RAMs, digital signal processing (DSP) blocks, and I/O pins fed by this clock.

The number of resources driven by every global clock and regional clock signal is reported in the Fan-out column of the Quartus® Prime Compilation Report. In the Compilation Report, select Fitter and click Place Stage. Select Global & Other Fast Signals Summary and observe the Fan-out value.

Note: Power consumed by Stratix® 10 MLAB clocks is accounted for in the RAM page; therefore, clock fanout on this page does not include any MLABs driven by this clock domain, for Stratix® 10 devices. For Agilex™ FPGA portfolio devices, MLAB is included in the fanout.
Global Enable % Enter the average percentage of time that the entire clock tree is enabled. Each global clock buffer has an enable signal that you can use to dynamically shut down the entire clock tree.
Local Enable %

Enter the average percentage of time that clock enable is high for destination flipflops.

Local clock enables for flipflops in ALMs are promoted to LAB-wide signals. When a given flipflop is disabled, the LAB-wide clock is disabled, cutting clock power and the power for down-stream logic. This page models only the impact on clock tree power.

Utilization Factor

Represents the impact of the clock network configuration on power.

Characteristics that have a large impact on power and are captured by this factor include the following:

  • Whether the network is widely spread out
  • Whether the fanout is small or large
  • The clock settings within each LAB

The default value for this field is typical; the actual value varies between clocks in your design, and depends on the placement of your design. For most accurate results, you should import this value from the Quartus® Prime software after compiling your design, because the Quartus® Prime software has access to detailed placement information.

In the absence of an Quartus® Prime design, higher values generally correspond to signals that span large distances on the FPGA and fanout to many destinations, while lower values correspond to more localized signals.

You can change this field from its default value to explore possible variations in power consumption depending on block placement. When changing this value, keep in mind that typical designs rarely use extreme values, and only for a small subset of the design.

Power (W) Indicates the total power dissipation due to clock distribution (in W).
User Comments Enter any comments. This is an optional entry.
Note: The Domain column which appeared in earlier versions of the PTC, is now the Full Hierarchy Name column. If you import a design file from a previous version of the PTC, any Domain entries will now appear in the Full Hierarchy Name column.

For more information about the clock networks of Agilex™ 7 devices, refer to the Agilex™ 7 Clocking and PLL User Guide.