5.8. Intel® FPGA PTC - PLL Page
Supported PLL types are family dependent, as outlined in the PLL Page Information table, below.
|Total thermal power (W)||Reports the total thermal power (in W).|
|fPLL utilization||Reports the percentage of fPLL utilization. (This field is available for Intel® Stratix® 10 devices only.)|
|IO PLL utilization||Reports the percentage of I/O PLL utilization.|
|ATX PLL utilization||Reports the percentage of ATX PLL utilization. (This field is available for Intel® Stratix® 10 devices only.)|
|CMU/CDR PLL utilization||Reports the percentage of CMU/CDR PLL utilization. (This field is available for Intel® Stratix® 10 devices only.)|
|Power rails||Indicated the voltage (mV), dynamic current (A), and standby current (A), for various power rails.|
|Module||Specify a name for the PLL in this column. This is an optional value.|
|Full Hierarchy Name||Specify the hierarchical path relevant to this entry. This is an optional entry. When entering levels of hierarchy, the pipe character (|) denotes a level of hierarchy.|
|PLL Type||Specifies the type of PLL, which may include the following:
|Bank ID||The I/O bank ID for this row. A bank location can be assigned to PLLs to change how the PLLs are placed, affecting thermals and utilization. (This column is available for Intel® Agilex™ devices only.)|
|# PLL Blocks||Enter the number of PLL blocks with the same combination of parameters.|
|XCVR Die ID||
Specify the transceiver die on which PLLs on this row are located. This field is not applicable for I/O PLLs, nor fabric-feeding I/O PLLs.
|# Counters||Enter the number of counters of the PLL.|
|VCCR_GXB and VCCT_GXB Voltage||Specify the voltage of the VCCR_GXB and VCCT_GXB rails. This field is not applicable for I/O PLLs, nor fabric-feeding I/O PLLs.|
|Output Freq (MHz)||Specify the output frequency for CMU and ATX PLLs.|
|VCO Freq (MHz)||Specify the internal VCO operating frequency for PLLs.|
|Total Power (W)||Shows the total estimated power for this row (in W).|
|User Comments||Enter any comments. This is an optional entry.|
For more information about the PLLs available in Intel® Agilex™ devices, refer to the Intel® Agilex™ Clocking and PLL User Guide.
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