5.9. Intel® FPGA PTC - I/O Page
The Intel® FPGA PTC assumes that you are using external termination resistors as recommended for SSTL and high-speed transceiver logic HSTL. If your design does not use external termination resistors, choose the LVTTL/ LVCMOS I/O standard with the same VCCIO and similar current strength as the terminated I/O standard.
To use on-chip termination (OCT), select the Current Strength/Output Termination option in the Intel® FPGA PTC.
The power reported for the I/O signals includes thermal and external I/O power. The total thermal power is the sum of the thermal power consumed by the device from each power rail, as shown in the following equation.
thermal power = thermal PVCCP + thermal PVCCPT + thermal PVCCIO
The following figure shows the I/O power consumption. The ICCIO power rail includes both the thermal PIO and the external PIO.
The VREF pins consume minimal current (typically less than 10 μA), which is negligible when compared with the current consumed by the general purpose I/O (GPIO) pins; therefore, the Intel® FPGA PTC does not include the current for VREF pins in the calculations.
|Voltage setting for unused GPIO Banks||Select a value to calculate voltage of unused GPIO banks. Available values are 1.2V, 1.5V, or Power Down Unused GPIO Banks.|
|Module||Specify a name for the I/O in this column. This is an optional value.|
|Full Hierarchy Name||Specify the hierarchical path relevant to this entry. This is an optional entry. When entering levels of hierarchy, the pipe character (|) denotes a level of hierarchy.|
|Application||Specify the application for this I/O row. GPIO and SerDes interfaces can be instantiated using this field. Use the I/O-IP page to instantiate external memory interface (EMIF) interfaces.|
|Bank Type||Specifies the type of I/O bank for this row.
|Bank ID||The I/O bank ID for this row. A bank location can be assigned to I/O pins to change how the I/O resources are placed, affecting thermals and utilization. (This column is available for Intel® Agilex™ devices only.)|
Specifies the clock rate of PHY logic. Determines the clock frequency of PHY logic in relation to the memory clock frequency.
For example, if the memory clock sent from the FPGA to the memory device is toggling at 800MHz, a quarter rate interface means that the PHY logic in the FPGA runs at 200MHz.
|I/O Standard||Specifies the I/O standard used by the I/O pins in this module.|
|Input Termination||Specifies the input termination setting for the input and bidirectional pins in this module.|
|Current Strength/Output Termination||Specifies the current strength or output termination setting for the output and bidirectional pins in this module. Current strength and output termination are mutually exclusive.|
|Slew Rate||Specifies the slew rate setting for the output and bidirectional pins in this module. Using a lower slew rate setting helps reduce switching noise but may increase delay.|
|VOD Setting||Specifies the differential output voltage (VOD) for the output and bidirectional pins in the module. A smaller number indicates a smaller VOD which reduces static power.|
|Pre-Emphasis Setting||Specifies the pre-emphasis setting for the output and bidirectional pins in this module. A smaller number indicates a smaller pre-emphasis which reduces dynamic power. (This column appears in the Intel® Stratix® 10 PTC only.)|
|Programmable De-Emphasis||Specifies the de-emphasis setting for the output and bidirectional pins in this module. A larger number indicates a smaller pre-emphasis which reduces dynamic power. (This column appears in the Intel® Agilex™ PTC only.)|
|Pin Direction||The pin's signal direction. Output, input, or bi-directional. (PTC for Intel® Agilex™ devices only.)|
|# Pins||Number of pins used in the specified configuration. (This column appears in the Intel® Agilex™ PTC only.)|
|# Input Pins||Specifies the number of input-only I/O pins in this module. Differential pin pairs count as one pin. (This column appears in the Intel® Stratix® 10 PTC only.)|
|# Output Pins||Specifies the number of output-only I/O pins in this module. Differential pin pairs count as one pin. (This column appears in the Intel® Stratix® 10 PTC only.)|
|# Bidir Pins||
Specifies the number of bidirectional I/O pins in this module. Differential pin pairs count as one pin. The I/O pin is treated as an output when its output enable signal is active and is treated as an input when the output enable signal is disabled.
An I/O pin configured as a bidirectional pin, but used only as an output, consumes more power than if it were configured as an output-only pin, due to the toggling of the input buffer every time the output buffer toggles (they share a common pin).
(This column appears in the Intel® Stratix® 10 PTC only.)
|Data Rate||Indicates whether I/O value changes once (Single-Data Rate) or twice (Double-Data Rate) per cycle.|
|Registered Pins||Indicates whether the pin is registered or not.|
|Toggle %||Percentage of clock cycles when the I/O signal changes value. This value is multiplied by clock frequency to determine the number of transitions per second. If DDR is selected, the toggle rate is multiplied by an additional factor of two.|
For modules with Input Termination set to OFF, enter the average percentage of time that:
During the remaining time:
Input Termination cannot be active while the Output I/O is enabled, so for modules with Input Termination not set to OFF, enter the average percentage of time that On-Chip Termination is inactive. (The average percentage of time that On-Chip Termination is inactive equals 100% minus the percentage of time that the On-Chip Termination is active.) This number must be a percentage between 0% and 100%.
|Load (pF)||Specifies pin loading external to the chip (in pF). Applies only to outputs and bidirectional pins. Pin and package capacitance is already included in the I/O model. Include only off-chip capacitance.|
|Pin Clock Frequency (MHz)||Clock frequency (in MHz). 100 MHz with a 12.5% toggle percentage would mean that each I/O pin toggles 12.5 million times per second (100 MHz * 12.5%).|
|Periphery Clock Freq (MHz)||
The I/O subsystem internal PHY clock frequency. This is an output-only field.
In SerDes applications, the PHY clock frequency is a function of the SerDes rate and serialization factor.
In external memory interface (EMIF) applications, the PHY clock frequency is a function of the memory clock frequency and DDR rate of the EMIF IP.
|VCO Clock Freq (MHz)||
The internal VCO operating frequency. This is an output-only field.
In SerDes applications, VCO frequency is a function of SerDes Data rate.
In external memory interface (EMIF) applications, the VCO frequency is a function of the memory clock frequency of the EMIF IP. The VCO frequency is not applicable in GPIO mode.
|Digital Power (W)||Power dissipated in the digital domain of the I/O-subsystem including GPIO, EMIF controller and SerDes controller.|
|Analog Power (W)||Power dissipated in the analog domain of the I/O-subsystem, for example, I/O buffers.|
Number of parallel data bits for each serial data bit. Used for SerDes-DPA.
|Data Rate (Mbps)||The maximum data rate of the SerDes channels in Mbps.|
|Mode||The DPA mode in which the SerDes channels are operating.|
|# of Channels||The number of channels running at the data rate of this SerDes domain.|
|User Comments||Enter any comments. This is an optional entry.|
For more information about the I/O standard termination schemes, refer to I/O and High Speed I/Os in Intel® Agilex™ Devices.
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