Intel® FPGA Power and Thermal Calculator User Guide

ID 683445
Date 9/26/2022
Public
Document Table of Contents

5.11.1. Estimating E-Tile Channel PLL Power with the Intel Power and Thermal Calculator

You can estimate E-tile channel PLL power for Intel® Stratix® 10 devices, by adding a Transmitter-only row to the Transceiver page of the Intel® FPGA Power and Thermal Calculator (PTC).

The following three examples illustrate the Intel® FPGA PTC configuration for various E-tile channel PLL requirements.

Table 18.  E-Tile Channel PLL configured for: Reference clock = 200MHz, pll_clkout1 = 800MHz, pll_clkout2 = 400MHz
Operation Mode Data Rate Digital/Analog Width Power Mode FEC EHIP Modulation Digital Freq # Refclks Refclk Freq VOD
Transmitter Only 12800 16 Normal Power Bypass Bypass NRZ 0 1 200 0
Table 19.  E-Tile Channel PLL configured for: Reference clock = 125MHz, pll_clkout1 = 500MHz, pll_clkout2 = 250MHz
Operation Mode Data Rate Digital/Analog Width Power Mode FEC EHIP Modulation Digital Freq # Refclks Refclk Freq VOD
Transmitter Only 8000 16 Normal Power Bypass Bypass NRZ 0 1 125 0
Table 20.  E-Tile Channel PLL configured for: Reference clock = 307MHz, pll_clkout1 = 491MHz, pll_clkout2 = 245MHz
Operation Mode Data Rate Digital/Analog Width Power Mode FEC EHIP Modulation Digital Freq # Refclks Refclk Freq VOD
Transmitter Only 19660.8 40 Normal Power Bypass Bypass NRZ 0 1 307 0

Alternatively, you can instantiate an E-Tile Transceiver-native PHY IP in PLL mode in your Intel® Quartus® Prime project, compile the project, and view the configuration in the Intel® FPGA PTC.

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