40Gbps Ethernet Accelerator Functional Unit (AFU) Design Example User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

ID 683436
Date 4/30/2019
Public

4. Using the Design Example as a Platform for Further Evaluation

Use the 40GbE AFU design example to perform further evaluation with the Intel FPGA MAC/PHY IP, third party IP, or your own MAC/PHY IP. The example design source is located in the same location as the sample AFUs included in the OPAE SDK installation:
$OPAE_PLATFORM_ROOT/hw/samples/eth_e2e_e40
The RTL source for the example is at the following location:
$OPAE_PLATFORM_ROOT/hw/samples/eth_e2e_e40/hw/rtl
While recompiling the example AFU to regenerate an AF (.gbs), you require an installed version of the Intel® Quartus® Prime Pro Edition (version 17.1.1) software.

OPAE version 1.0.2 does not support the ASE flow for HSSI interfaces.

Did you find the information on this page useful?

Characters remaining:

Feedback Message