4. Using the Design Example as a Platform for Further Evaluation
Use the 40GbE AFU design example to perform further evaluation with the Intel FPGA MAC/PHY IP, third party IP, or your own MAC/PHY IP. The example design source is located in the same location as the sample AFUs included in the OPAE SDK installation:
The RTL source for the example is at the following location:
While recompiling the example AFU to regenerate an AF (.gbs), you require an installed version of the Intel® Quartus® Prime Pro Edition (version 17.1.1) software.
OPAE version 1.0.2 does not support the ASE flow for HSSI interfaces.