40Gbps Ethernet Accelerator Functional Unit (AFU) Design Example User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

ID 683436
Date 4/30/2019
Public

2. Overview

The 40Gbps Ethernet (40GbE) AFU design example in the Acceleration Stack installation allows you to evaluate the network port capabilities of the Intel® PAC with Intel® Arria® 10 GX FPGA. The 40GbE AFU design example contains a 40GbE MAC instance with traffic generation and checking logic to send and receive ethernet packets on the QSFP+ network port. The Acceleration Stack installation includes OPAE tools, APIs and a sample host application to initialize and start packet transfers from the host, and subsequently retrieve port statistics.

This design example supports internal HSSI transceiver loopback, external QSFP+ port loopback, and Intel® PAC-to-PAC modes of operation.
Figure 1. System Block Diagram

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