40Gbps Ethernet Accelerator Functional Unit (AFU) Design Example User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683436
Date 4/30/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Overview 3. Running the Design Example Tests 4. Using the Design Example as a Platform for Further Evaluation 5. 40Gbps Ethernet AFU Design Example User Guide Archives 6. Document Revision History for 40Gbps Ethernet AFU Design Example User Guide
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronym List 1.4. Acceleration Glossary
2. Overview x
2.1. 40GbE Design Example AFU Hardware 2.2. 40GbE Design Example AFU Software
3. Running the Design Example Tests x
3.1. Setup Prerequisites 3.2. Running 40GbE Internal Loopback Test in Single Intel® PAC System 3.3. Running 40GbE External Loopback Test in Single Intel® PAC System 3.4. Running 40GbE Intel® PAC-to-PAC Test between two connected Intel® PACs
4. Using the Design Example as a Platform for Further Evaluation x
4.1. Prerequisite while Evaluating with the Intel FPGA MAC/PHY IP 4.2. Evaluation with an Alternate MAC/PHY IP
1. About this Document
2. Overview
3. Running the Design Example Tests
4. Using the Design Example as a Platform for Further Evaluation
5. 40Gbps Ethernet AFU Design Example User Guide Archives
6. Document Revision History for 40Gbps Ethernet AFU Design Example User Guide

1.1. Intended Audience

This document is intended for AFU developers and systems engineers to use as a quick start guide for evaluating AFU design and system integration of the network port feature on the Intel® PAC with Intel® Arria® 10 GX FPGA.

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