40Gbps Ethernet Accelerator Functional Unit (AFU) Design Example User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683436
Date 4/30/2019
Public
Document Table of Contents
Document Table of Contents
1. About this Document 2. Overview 3. Running the Design Example Tests 4. Using the Design Example as a Platform for Further Evaluation 5. 40Gbps Ethernet AFU Design Example User Guide Archives 6. Document Revision History for 40Gbps Ethernet AFU Design Example User Guide
1. About this Document
1.1. Intended Audience 1.2. Conventions 1.3. Acronym List 1.4. Acceleration Glossary
2. Overview
2.1. 40GbE Design Example AFU Hardware 2.2. 40GbE Design Example AFU Software
3. Running the Design Example Tests
3.1. Setup Prerequisites 3.2. Running 40GbE Internal Loopback Test in Single Intel® PAC System 3.3. Running 40GbE External Loopback Test in Single Intel® PAC System 3.4. Running 40GbE Intel® PAC-to-PAC Test between two connected Intel® PACs
4. Using the Design Example as a Platform for Further Evaluation
4.1. Prerequisite while Evaluating with the Intel FPGA MAC/PHY IP 4.2. Evaluation with an Alternate MAC/PHY IP
1. About this Document
2. Overview
3. Running the Design Example Tests
4. Using the Design Example as a Platform for Further Evaluation
5. 40Gbps Ethernet AFU Design Example User Guide Archives
6. Document Revision History for 40Gbps Ethernet AFU Design Example User Guide

4.2. Evaluation with an Alternate MAC/PHY IP

You can use the 40GbE AFU example as a framework to evaluate MAC/PHY IP from third parties or your own IP. The design example instantiates the Intel FPGA MAC/PHY IP in the following AFU RTL source file: 
OPAE_PLATFORM_ROOT/hw/samples/eth_e2e_e40/hw/rtl/eth_e2e_e40.v

Replace the alt_eth_ultra_0 instance shown in this figure with your own MAC/PHY IP instance. You must provide any necessary wrapper shim logic to integrate your IP within the AFU design example framework.

Figure 4. 40GbE AFU Design Example Hierarchy
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