Stratix® 10 Embedded Memory User Guide

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ID 683423
Date 7/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 Embedded Memory Overview 2. Stratix® 10 Embedded Memory Architecture and Features 3. Stratix® 10 Embedded Memory Design Considerations 4. Stratix® 10 Embedded Memory IP References 5. Stratix 10 Embedded Memory Design Example 6. Stratix® 10 Embedded Memory User Guide Archives 7. Document Revision History for the Stratix® 10 Embedded Memory User Guide
1. Stratix® 10 Embedded Memory Overview x
1.1. Stratix® 10 Embedded Memory Features
2. Stratix® 10 Embedded Memory Architecture and Features x
2.1. Byte Enable in Stratix® 10 Embedded Memory Blocks 2.2. Address Clock Enable Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code (ECC) Support 2.5. Force-to-Zero 2.6. Coherent Read Memory 2.7. Freeze Logic 2.8. True Dual Port Dual Clock Emulator 2.9. 'X' Propagation Support in Simulation 2.10. Stratix® 10 Supported Embedded Memory IPs 2.11. Stratix® 10 Embedded Memory Clocking Modes 2.12. Stratix® 10 Embedded Memory Configurations 2.13. Initial Value of Read and Write Address Registers
2.1. Byte Enable in Stratix® 10 Embedded Memory Blocks x
2.1.1. Byte Enable Controls 2.1.2. Data Byte Output 2.1.3. Byte Enable Behavior
2.4. Memory Blocks Error Correction Code (ECC) Support x
2.4.1. Parity Bit 2.4.2. ECC Parity Flip 2.4.3. ECC Read-During-Write Behavior 2.4.4. Error Correction Code Truth Table
2.6. Coherent Read Memory x
2.6.1. Forwarding Logic
2.8. True Dual Port Dual Clock Emulator x
2.8.1. Reducing the DCFIFO Depth 2.8.2. True Dual-Port Mixed Port Read During Write New Data Emulation
2.11. Stratix® 10 Embedded Memory Clocking Modes x
2.11.1. Single Clock Mode 2.11.2. Read/Write Clock Mode 2.11.3. Input/Output Clock Mode 2.11.4. Asynchronous/Synchronous Clears in Clocking Modes 2.11.5. Output Read Data in Simultaneous Read/Write 2.11.6. Independent Clock Enables in Clocking Modes
2.12. Stratix® 10 Embedded Memory Configurations x
2.12.1. Mixed-Width Port Configurations
3. Stratix® 10 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Read Behavior 3.3. Read-During-Write (RDW) 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Including the Reset Release FPGA IP in Your Design 3.9. Resource and Timing Optimization Feature in MLAB Blocks 3.10. Consider the Memory Depth Setting 3.11. Consider Registering the Memory Output
3.3. Read-During-Write (RDW) x
3.3.1. Customize Read-During-Write Behavior
3.3.1. Customize Read-During-Write Behavior x
3.3.1.1. Same-Port Read-During-Write Mode 3.3.1.2. Mixed-Port Read-During-Write Mode
4. Stratix® 10 Embedded Memory IP References x
4.1. On Chip Memory RAM and ROM FPGA IPs 4.2. eSRAM FPGA IP 4.3. FIFO IP 4.4. FIFO2 IP 4.5. Shift Register (RAM-based) FPGA IP
4.1. On Chip Memory RAM and ROM FPGA IPs x
4.1.1. Release Information for RAM and ROM IPs 4.1.2. RAM: 1-PORT FPGA IP Parameters 4.1.3. RAM: 2-PORT FPGA IP Parameters 4.1.4. RAM: 4-PORT FPGA IP Parameters 4.1.5. ROM: 1-PORT FPGA IP Parameters 4.1.6. ROM: 2-PORT FPGA IP Parameters 4.1.7. RAM and ROM Interface Signals 4.1.8. Changing Parameter Settings Manually
4.1.8. Changing Parameter Settings Manually x
4.1.8.1. RAM and ROM Parameter Settings
4.2. eSRAM FPGA IP x
4.2.1. Release Information for eSRAM FPGA IP 4.2.2. eSRAM System Features 4.2.3. eSRAM FPGA IP Parameters 4.2.4. eSRAM FPGA IP Interface Signals 4.2.5. eSRAM FPGA IP Simulation Walk-Through 4.2.6. eSRAM Timing Diagrams
4.2.2. eSRAM System Features x
4.2.2.1. eSRAM Specifications 4.2.2.2. eSRAM Usage Model
4.3. FIFO IP x
4.3.1. Release Information for FIFO FPGA IP 4.3.2. Configuration Methods 4.3.3. Specifications 4.3.4. FIFO Functional Timing Requirements 4.3.5. SCFIFO ALMOST_EMPTY Functional Timing 4.3.6. FIFO Output Status Flag and Latency 4.3.7. FIFO Metastability Protection and Related Options 4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.3.9. SCFIFO and DCFIFO Show-Ahead Mode 4.3.10. Different Input and Output Width 4.3.11. DCFIFO Timing Constraint Setting 4.3.12. Coding Example for Manual Instantiation 4.3.13. Design Example 4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing 4.3.15. Guidelines for Embedded Memory ECC Feature 4.3.16. FIFO IP Parameters 4.3.17. Reset Scheme
4.3.3. Specifications x
4.3.3.1. Verilog HDL Prototype 4.3.3.2. VHDL Component Declaration 4.3.3.3. VHDL LIBRARY-USE Declaration 4.3.3.4. FIFO Signals 4.3.3.5. FIFO Parameter Settings
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.3.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.3.11. DCFIFO Timing Constraint Setting x
4.3.11.1. Embedded Timing Constraint 4.3.11.2. User Configurable Timing Constraint
4.3.11.2. User Configurable Timing Constraint x
4.3.11.2.1. SDC Commands
4.4. FIFO2 IP x
4.4.1. Release Information for FIFO2 IP 4.4.2. Configuration Methods 4.4.3. Fmax Target Measuring Methodology 4.4.4. Performance Considerations 4.4.5. FIFO2 IP Features 4.4.6. FIFO2 IP Parameters 4.4.7. FIFO2 IP Interface Signals 4.4.8. Reset and Clock Schemes
4.4.5. FIFO2 IP Features x
4.4.5.1. FIFO2 Specifications
4.4.6. FIFO2 IP Parameters x
4.4.6.1. FIFO2 Parameter Settings
4.4.7. FIFO2 IP Interface Signals x
4.4.7.1. SCFIFO Signals 4.4.7.2. DCFIFO Signals
4.4.8. Reset and Clock Schemes x
4.4.8.1. Clock Domains 4.4.8.2. Reset
4.4.8.2. Reset x
4.4.8.2.1. FIFO2 IP Reset Guidelines
4.5. Shift Register (RAM-based) FPGA IP x
4.5.1. Release Information for Shift Register (RAM-based) FPGA IP 4.5.2. Shift Register (RAM-based) FPGA IP Features 4.5.3. Shift Register (RAM-based) FPGA IP General Description 4.5.4. Shift Register (RAM-based) FPGA IP Parameter Settings 4.5.5. Shift Register Ports and Parameters Setting
5. Stratix 10 Embedded Memory Design Example x
5.1. FIFO and FIFO2 Design Example
5.1. FIFO and FIFO2 Design Example x
5.1.1. Generating the Design Example 5.1.2. Simulating the Design Example
5.1.2. Simulating the Design Example x
5.1.2.1. Simulation Results
1. Stratix® 10 Embedded Memory Overview
2. Stratix® 10 Embedded Memory Architecture and Features
3. Stratix® 10 Embedded Memory Design Considerations
4. Stratix® 10 Embedded Memory IP References
5. Stratix 10 Embedded Memory Design Example
6. Stratix® 10 Embedded Memory User Guide Archives
7. Document Revision History for the Stratix® 10 Embedded Memory User Guide

4.1.5. ROM: 1-PORT FPGA IP Parameters

Table 43.   ROM: 1-PORT FPGA IP Parameters—Widths/Blk Type/Clks Tab
Parameter Legal Values Description
How wide should the 'q' output bus be? — Specifies the width of the 'q' output bus.
How many words of memory? — Specifies the number of words.
What should the memory block type be? Auto, MLAB, M20K Specifies the memory block type. The types of memory block that are available for selection depends on your target device.
Set the maximum block depth to
  • MLAB: Auto, 32
  • M20K: Auto, 512, 1024, 2048
 Specifies the maximum block depth in words.
Which clocking method would you like to use?
  • Single clock
  • Dual clock: use separate 'input' and 'output' clocks

Specifies the clocking method to use.

  • Single clock—A single clock and a clock enable controls all registers of the memory block
  • Dual clock: use separate 'input' and 'output' clocks—The input clock controls the address registers and the output clock controls the data-out registers. There are no write-enable, byte-enable, or data-in registers in ROM mode.
Table 44.   ROM: 1-PORT FPGA IP Parameters—Regs/Clken/Aclrs Tab
Parameter Legal Values Description

'address' input port

 On/Off Specifies whether to register the input and output ports.
'q' output port
Use clock enable for port A input registers On/Off Specifies whether to use clock enable for port A input registers.
Use clock enable for port A output registers On/Off Specifies whether to use clock enable for port A output registers.
Create an 'addressstall_a' input port On/Off Specifies whether to create an addressstall_a input port. You can create this port to act as an extra active low clock enable input for the address registers.
Which registered ports should be affected by the 'aclr' port? 'q' port On/Off Specifies whether the registered port is affected by an asynchronous clear port.
Create a 'sclr' asynchronous clear for the registered ports. 'q' port On/Off Specifies whether the q port is affected by a synchronous clear port.
Create an 'rden' read enable signal On/Off Specifies whether to create a read enable signal.
Table 45.   ROM: 1-PORT FPGA IP Parameters—Mem Init Tab
Parameter Legal Values Description
Parameter Settings:    
Do you want to specify the initial content of the memory?
  • No, leave it blank
  • Yes, use this file for the memory content data

Specifies the initial content of the memory.

In ROM mode, you must specify a memory initialization file (.mif) or a hexadecimal (Altera format) file (.hex). The default option is Yes, use this file for the memory content data.
File name — Specify a file name if initial content of the memory is not set to blank. The file must be in .hex or .mif format.
The initial content file should conform to which port's dimensions? PORT_A The initial content file for memory content data only conforms to port A.
Allow In-System Memory Content Editor to capture and update content independently of the system clock On/Off Specifies whether to allow In-System Memory Content Editor to capture and update content independently of the system clock
The 'Instance ID' of this ROM is NONE Specifies the ROM ID.
Table 46.   ROM: 1-PORT FPGA IP Parameters—Performance Optimization Tab
Parameter Legal Values Description
Enable Force-to-Zero On/Off Specifies whether to set the output to zero when you deassert the read enable signal.

Enabling this feature helps improve the glue logic performance when the selected memory depth is larger than a single memory block.
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