AN 719: Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report

ID 683421
Date 9/22/2014

1.2. Hardware Setup

A Stratix V Advanced Systems Development Kit is used with the TI DAC37J84 daughter card module installed to the development board’s FMC connector.

  • The DAC37J84 EVM derives power from 5.0 V power adaptor.
  • The FPGA and DAC device clock is supplied by the LMK04828 clock generator on the DAC37J84 EVM.
  • For subclass 1, the LMK04828 clock generator generates SYSREF for the JESD204B IP core as well as the DAC37J84 device.
  • The sync_n signal is transmitted from the DAC37J84 to FPGA through a wire connected to J21 (pin 1) of DAC37J84 EVM and HSMC breakout board (pin 3). 1
Figure 1. Hardware Setup

Figure 2. System Diagram

The system-level diagram shows how the different modules connect in this design.

In this setup, where LMF = 841, the data rate of transceiver lanes is 12.288 Gbps. The LMK04828 clock generator provides 307.2 MHz device clock to the FPGA and 1228.8 MHz device clock to the DAC37J84 device. The LMK04828 provides SYSREF pulses to both the DAC and FPGA. A wire connects between J21 pin 1 on DAC37J84 EVM (SYNC_N_AB pin) and HSMC breakout board header pin 3 to transmit the sync_n signal from DAC37J84 to FPGA 2. The FPGA 2 acts as a passthrough to deliver sync_n signal to FPGA 1. The DAC37J84 operates in LINK0 only mode (single link) in all configurations.

Note: The FPGA 2 must be configured prior to connecting the wire that carries the sync_n signal to the HSMC breakout board header. Verify that the voltage at the targeted header pin is less than 1.8 V. Refer to the DAC37J84 datasheet for the absolute maximum rating of SYNC_N_AB pin.
1 The sync_n signal from the DAC does not have direct connection to FPGA 1 through the FMC connector. The FPGA 2 is used as a bridge to transfer the sync_n signal to FPGA 1 through the HSMC connector.