AN 719: Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report

ID 683421
Date 9/22/2014

1.7. Test Result Comments

In each test case, the TX JESD204B IP core successfully initializes from CGS phase, ILA phase, and until user data phase. The jesd204_tx_int signal is asserted because the DAC deasserts sync_n initially and then asserts sync_n for a duration of more than 5 frames plus 9 octets. The sync_reinit_req bit of tx_err register (bit 4) is set. Since there is no register available at the DAC to set the initial logic level of sync_n signal, the jesd204_tx_int signal is asserted during link initialization. There is no other error bit being set in the tx_err register throughout CGS.2 and ILAS.1- 3 test cases. Other than the TX interrupt, the behavior of the TX JESD204B IP core meets the passing criteria. To clear the interrupt, write “1” to tx_err (bit 4) register. From the DAC3XJ8X Controls > Alarms and Errors tab in DAC3XJ8XEVM GUI, no error pertaining to RX JESD204B IP core is reported.

For LMF=148 configuration, 9.8304 Gbps is the highest data rate achievable using the EVM on-board clocking mode; the period of SYSREF pulses for K=32 configuration needs to be 1 LMFC in order to get a stable link initialization.

No data integrity issue is observed from the short transport layer test pattern checkers at DAC JESD core. Sine wave is observed at all four analog channels when sine wave generators in FPGA are enabled.

In the deterministic latency measurement, consistent total latency is observed across the JESD204B link and DAC analog channels.