AN 719: Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report

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ID 683421
Date 9/22/2014
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Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report
1. Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. DAC3XJ8XEVM Software Setup 1.4. Hardware Checkout Methodology 1.5. JESD204B IP Core and DAC37J84 Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. AN 719 Document Revision History
1.4. Hardware Checkout Methodology x
1.4.1. Transmitter Data Link Layer 1.4.2. Transmitter Transport Layer 1.4.3. Scrambling 1.4.4. Deterministic Latency (Subclass 1)
1.4.1. Transmitter Data Link Layer x
1.4.1.1. Code Group Synchronization (CGS) 1.4.1.2. Initial Lane Alignment Sequence (ILAS)
1. Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report

1.4.2. Transmitter Transport Layer

To verify the data integrity of the payload data stream through the TX JESD204B IP core and transport layer, the DAC JESD core is configured to check short transport layer test pattern that is transmitted from FPGA test pattern generator. The DAC JESD core checks the short transport layer test patterns based on F = 1, 2, 4 or 8 configuration. Refer to Table for the short transport layer test pattern configuration. The short test pattern has a duration of one frame period and is repeated continuously for the duration of the test.

To verify that data from the FPGA digital domain is successfully sent to the DAC analog domain, the FPGA is configured to generate a sine wave. Connect an oscilloscope to observe the waveform at the DAC analog channels.

Figure 11.  Data Integrity Check Using DAC Short Transport Layer Pattern CheckerThis figure shows the conceptual test setup for short transport layer data integrity checking.


The SignalTap II Logic Analyzer tool monitors the operation of the TX transport layer.

Table 3.  Transport Layer Test Cases

Test Case

Objective

Description

Passing Criteria

TL.1

Check the transport layer mapping using short transport layer test pattern as specified in the parameter configuration.

The following signals in altera_jesd204_transport_tx_top.sv are tapped:

  • jesd204_tx_data_valid
  • jesd204_tx_data_ready

The following signal in jesd204b_ed.sv is tapped:

  • jesd204_tx_int

The txframe_clk is used as the SignalTap II sampling clock. 5

Check the following error in “Alarm and Errors” tab in the DAC3XJ8XEVM GUI:

  • Short Test Error
  • The jesd204_tx_data_ready and jesd204_tx_data_valid signals are asserted.
  • The “Short Test Error” is not asserted.

TL.2

Verify the data transfer from digital to analog domain.

Enable sine wave generator in the FPGA and observe the DAC analog channel output on the oscilloscope.

A monotone sine wave is observed on the oscilloscope.

5 For LMF=148 configuration, the txlink_clk signal is used as the SignalTap II sampling clock as the txlink_clk frequency is two times of the txframe_clk frequency.
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