ILA.1

Check that /R/ and /A/ characters are transmitted at the beginning and end of each multiframe. Verify that four multiframes are transmitted in ILAS phase and receiver detects the initial lane alignment sequence correctly.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

• jesd204_tx_pcs_data[(L*32)-1:0]
• jesd204_rx_pcs_kchar_data[(L*4)-1:0] ³

The following signals in <ip_variant_name>.v are tapped:

• sync_n
• jesd204_tx_int

The txlink_clk is used as the SignalTap II sampling clock.

Each lane is represented by 32-bit data bus in the jesd204_tx_pcs_data signal. The 32-bit data bus is divided into 4 octets.

Check the following error in “Alarm and Errors” tab in the DAC3XJ8XEVM GUI:

• Frame Alignment Error
• Multiframe Alignment Error

• The /R/ character or K28.0 (0x1C) is transmitted at the jesd204_tx_pcs_data bus to mark the beginning of multiframe.
• The /A/ character or K28.3 (0x7C) is transmitted at the jesd204_tx_pcs_data bus to mark the end of each multiframe.
• The sync_n and jesd204_tx_int signals are deasserted.
• The jesd204_tx_pcs_kchar_data signal is asserted whenever control characters like /K/, /R/, /Q/ or /A/ characters are transmitted.
• The “Frame Alignment Error” and “Multiframe Alignment Error” in the GUI are not asserted.

ILA.2

Check the JESD204B configuration parameters are transmitted in the second multiframe.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

• jesd204_tx_pcs_data[(L*32)-1:0] ³

The following signal in <ip_variant_name>.v is tapped:

• jesd204_tx_int

The txlink_clk is used as the SignalTap II sampling clock.

The system console accesses the following registers:

• ilas_data0
• ilas_data1
• ilas_data2
• ilas_data4
• ilas_data5

The content of 14 configuration octets in the second multiframe is stored in these 32-bit registers - ilas_data0, ilas_data1, ilas_data2, ilas_data4 and ilas_data5.

Check the following error in “Alarm and Errors” tab in the DAC3XJ8XEVM GUI:

• Link Configuration Error

• The /R/ character is followed by /Q/ character or K28.4 (0x9C) in the jesd204_tx_pcs_data bus at the beginning of second multiframe.
• The JESD204B parameters read from ilas_data0, ilas_data1, ilas_data2, ilas_data4, and ilas_data5 registers are the same as the parameters set in the JESD204B IP core Qsys parameter editor.
• The jesd204_tx_int signal is deasserted if there is no error.
• The “Link Configuration Error” in the GUI is not asserted.

ILA.3

Check the constant pattern of transmitted user data after the end of 4th multiframes. Verify that the receiver successfully enters user data phase.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

• jesd204_tx_pcs_data[(L*32)-1:0]

The following signal in <ip_variant_name>.v is tapped:

• jesd204_tx_int

The txlink_clk is used as the SignalTap II sampling clock.

The system console accesses the tx_err register.

Check the following errors in the Alarm and Errors tab in the DAC3XJ8XEVM GUI:

• Elastic Buffer Overflow
• Elastic Buffer Match Error

• When scrambler is turned off, the first user data is transmitted after the last /A/ character, which marks the end of the 4th multiframe transmitted. ⁴
• The jesd204_tx_int signal is deasserted if there is no error.
• Bits 2 and 3 of the tx_err register are not set to “1”.
• The “Elastic Buffer Overflow” and “Elastic Buffer Match Error” in the GUI are not asserted.