AN 719: Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report

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ID 683421
Date 9/22/2014
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Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report
1. Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. DAC3XJ8XEVM Software Setup 1.4. Hardware Checkout Methodology 1.5. JESD204B IP Core and DAC37J84 Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. AN 719 Document Revision History
1.4. Hardware Checkout Methodology x
1.4.1. Transmitter Data Link Layer 1.4.2. Transmitter Transport Layer 1.4.3. Scrambling 1.4.4. Deterministic Latency (Subclass 1)
1.4.1. Transmitter Data Link Layer x
1.4.1.1. Code Group Synchronization (CGS) 1.4.1.2. Initial Lane Alignment Sequence (ILAS)
1. Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report

1.6. Test Results

The following table contains the possible results and their definition.

Table 7.  Results Definition

Result

Definition

PASS

The Device Under Test (DUT) was observed to exhibit conformant behavior.

PASS with comments

The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included, such as due to time limitations only a portion of the testing was performed.

FAIL

The DUT was observed to exhibit non-conformant behavior.

Warning

The DUT was observed to exhibit behavior that is not recommended.

Refer to comments

From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included.

The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, TL.2, SCR.1 and SCR.2 with different values of L, M, F, SCR, K, data rate, DAC output rate, FPGA link clock and sysref pulse frequency.

Table 8.  Test Results

Test

L

M

F

SCR

K

Data rate (Mbps)

DAC Output Rate (MSPS)

FPGA Link Clock (MHz)

Sysref Pulse Frequency (MHz)

Result

1

1

4

8

0

16

9830.4

983.04

245.76

3.84

Pass with comments

2

1

4

8

1

16

9830.4

983.04

245.76

3.84

Pass with comments

3

1

4

8

0

32

9830.4

983.04

245.76

3.84

Pass with comments

4

1

4

8

1

32

9830.4

983.04

245.76

3.84

Pass with comments

5

2

4

4

0

16

12288

1228.8

307.2

9.6

Pass with comments

6

2

4

4

1

16

12288

1228.8

307.2

9.6

Pass with comments

7

2

4

4

0

32

12288

1228.8

307.2

4.8

Pass with comments

8

2

4

4

1

32

12288

1228.8

307.2

4.8

Pass with comments

9

4

4

2

0

16

12288

1228.8

307.2

19.2

Pass with comments

10

4

4

2

1

16

12288

1228.8

307.2

19.2

Pass with comments

11

4

4

2

0

32

12288

1228.8

307.2

9.6

Pass with comments

12

4

4

2

1

32

12288

1228.8

307.2

9.6

Pass with comments

13

8

4

1

0

20

12288

1228.8

307.2

20.48

Pass with comments

14

8

4

1

1

20

12288

1228.8

307.2

20.48

Pass with comments

15

8

4

1

0

32

12288

1228.8

307.2

19.2

Pass with comments

16

8

4

1

1

32

12288

1228.8

307.2

19.2

Pass with comments

Table 9.  Test Results For Deterministic Latency

Test

L

M

F

SCR

K

RBD 13

Data rate (Mbps)

DAC Output Rate (MSPS)

FPGA Link Clock (MHz)

Total Latency Result

DL.1

1

4

8

1

32

31

9830.4

983.04

245.76

Pass, ~810.8–811.2 ns

DL.2

1

4

8

1

32

31

9830.4

983.04

245.76

Pass, ~810.9–811.3 ns

DL.1

2

4

4

1

32

31

12288

1228.8

307.2

Pass, ~391.5–391.7 ns

DL.2

2

4

4

1

32

31

12288

1228.8

307.2

Pass, ~391.4–391.6 ns

DL.1

4

4

2

1

32

31

12288

1228.8

307.2

Pass, ~279.1–279.2 ns

DL.2

4

4

2

1

32

31

12288

1228.8

307.2

Pass, ~279.1–279.3 ns

DL.1

8

4

1

1

32

31

12288

1228.8

307.2

Pass, ~215.6–215.8 ns

DL.2

8

4

1

1

32

31

12288

1228.8

307.2

Pass, ~215.6–215.8 ns

Figure shows the results of the alarm and error checking at DAC3XJ8XEVM GUI for LMF = 841 configuration. No link initialization alarm or error is reported.

Figure 13.  Sine wave at DAC analog channel output

Figure shows the sine wave output from DAC analog channel.



Figure 14.  Deterministic Latency Measurement For LMF = 442 Configuration

Figure shows the time difference between pulses in deterministic latency measurement for LMF = 442 configuration.



13 Set the RBD value in the DAC3XJ8XEVM GUI.
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