AN 719: Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report

ID 683421
Date 9/22/2014
Public

1.4.3. Scrambling

With descrambler enabled, the short transport layer test pattern checker at the DAC JESD core checks the data integrity of scrambler in the FPGA.

The SignalTap II Logic Analyzer tool monitors the operation of the TX transport layer.

Table 4.  Descrambler Test Cases

Test Case

Objective

Description

Passing Criteria

SCR.1

Check the functionality of the scrambler using short transport layer test pattern as specified in the parameter configuration.

Enable descrambler at the DAC JESD core and scrambler at the TX JESD204B IP core.

The signals that are tapped in this test case are similar to test case TL.1

Check the following error in “Alarm and Errors” tab in the DAC3XJ8XEVM GUI:

  • Short Test Error
  • The jesd204_tx_data_ready and jesd204_tx_data_valid signals are asserted.
  • The “Short Test Error” is not asserted.

SCR.2

Verify the data transfer from digital to analog domain.

Enable descrambler at the DAC JESD core and scrambler at the TX JESD204B IP core.

Enable sine wave generator in the FPGA and observe the DAC analog channel output on the oscilloscope.

A monotone sine wave is observed on the oscilloscope.

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