Generic Serial Flash Interface Intel® FPGA IP User Guide

ID 683419
Date 4/01/2024
Document Table of Contents

1.4. Parameters

Table 3.  Parameter Settings - General Tab
Parameter Legal Values Descriptions
General Settings
Device Density (Mb) 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048 Density of the flash device used in Mb.
Disable dedicated Active Serial interface Routes the signals to the top level of your design. Enable this when you want to include the Serial Flash Loader Intel FPGA IP in your design.
Enable SPI pins interface Translates the signals to the SPI pin interface.
Number of Chip Select used




Selects the number of chip select connected to the flash.
Default Settings
Control Register - Expose the default settings for the Control Register. Refer to Register Map for the legal values and bit field descriptions.
Debug Mode
Advance Mode


Enable the Advanced Mode tab which expose the default settings for all registers.
Table 4.  Parameter Settings - Simulation Tab
Parameter Legal Values Descriptions
Enable Simulation - Uses the default EPCQ1024 simulation model for simulation. When disabled, refer to AN-720: Simulating the ASMI Block in Your Design for creating a wrapper to use with other flash simulation model.
Note: When modifying the register settings in Advanced Mode tab, Refer to Register Map table for the legal values and parameter descriptions.