Generic Serial Flash Interface Intel® FPGA IP User Guide

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ID 683419
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Generic Serial Flash Interface Intel® FPGA IP User Guide
1. Generic Serial Flash Interface Intel® FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Signals 1.4. Parameters 1.5. Register Map 1.6. Using Generic Serial Flash Interface Intel® FPGA IP 1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design 1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP 1.9. Intel HAL Driver 1.10. Generic Serial Flash Interface Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide
1.6. Using Generic Serial Flash Interface Intel® FPGA IP x
1.6.1. Control Status Register Byte Enable 1.6.2. Memory Operations 1.6.3. Byte Enabling 1.6.4. Constraining the I/O Pins
1.6.3. Byte Enabling x
1.6.3.1. Byte Enabling Supported Patterns
1.6.4. Constraining the I/O Pins x
1.6.4.1. General Purpose I/O 1.6.4.2. Dedicated Active Serial Interface
1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design x
1.7.1. Hardware and Software Requirements 1.7.2. Functional Description 1.7.3. Creating Nios® II Hardware System 1.7.4. Integrating Modules into Quartus® Prime Project 1.7.5. Programming the .sof File 1.7.6. Building Application Software System using Nios® II Software Build Tools
1.7.2. Functional Description x
1.7.2.1. Reference Design Components 1.7.2.2. Reference Design Application Program
1.7.6. Building Application Software System using Nios® II Software Build Tools x
1.7.6.1. Reference Design Results
1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP x
1.8.1. Flash Operations that Require Operation Code 1.8.2. Flash Operations to Read Flash Registers 1.8.3. Flash Operations to Write Flash Registers 1.8.4. Flash Operations that Require An Address 1.8.5. Read Memory from the Flash 1.8.6. Program Flash
1.9. Intel HAL Driver x
1.9.1. Driver API
1. Generic Serial Flash Interface Intel® FPGA IP User Guide

1.4. Parameters

Table 3.  Parameter Settings - General Tab
Parameter Legal Values Descriptions
General Settings
Device Density (Mb) 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048 Density of the flash device used in Mb.
Disable dedicated Active Serial interface — Routes the signals to the top level of your design. Enable this when you want to include the Serial Flash Loader Intel FPGA IP in your design.
Enable SPI pins interface — Translates the signals to the SPI pin interface.
Number of Chip Select used

1

2

3

 Selects the number of chip select connected to the flash.
Default Settings
Control Register - Expose the default settings for the Control Register. Refer to Register Map for the legal values and bit field descriptions.
Debug Mode
Advance Mode

Disabled

Enabled 		Enable the Advanced Mode tab which expose the default settings for all registers.
Table 4.  Parameter Settings - Simulation Tab
Parameter Legal Values Descriptions
Enable Simulation - Uses the default EPCQ1024 simulation model for simulation. When disabled, refer to AN-720: Simulating the ASMI Block in Your Design for creating a wrapper to use with other flash simulation model.
Note: When modifying the register settings in Advanced Mode tab, Refer to Register Map table for the legal values and parameter descriptions.
Related Information
Level Two Title