Generic Serial Flash Interface Intel® FPGA IP User Guide

ID 683419
Date 4/01/2024
Document Table of Contents

1.6.1. Control Status Register Byte Enable

The byte enable for the Control Status Register (CSR) interface feature allows you to write to all CSRs, from 0x0 to 0xD, in the Generic Serial Flash Interface Intel® FPGA IP while selecting only certain bytes to write.

The avl_csr_byteenable port provides support for this feature.

  • For normal CSRs (all CSRs except write data registers, 0xA and 0xB), the CSRs retain their values if a particular byteenable is not enabled, and only write the new value for enabled bytes.
  • The writedata CSRs (0xA and 0xB) store the write data to target flash. The IP only writes enabled bytes with the corresponding data and does not retain the old values for disabled bytes.
    • The IP writes the writedata for all valid enabled bytes into the flash at a specified starting address as the first data.
    • Set the correct number of data bytes register in bit[15:12] in the flash command setting register (0x7). If you intend to write both write data 0 and write data 1 into the flash, you must write the number of data bytes to 8, regardless of how many CSR byteenable bits are set. The IP writes the enabled byte as the first data into the starting address for write data 0, and then fills the rest of the bytes for write data 0 as FF. The IP does the same for write data 1. If you intend to write one write data 0 or write data 1 into flash, you must set the number of data bytes to the same as avl_csr_byteeanable bytes. In other words, if you enable 2 bytes in avl_csr_byteenable (4'b0110), the number of data bytes to be sent is also 2 bytes. The IP writes only the enabled data directly into the address that you specified in the flash command address register (0x9).

You have the option to turn on Use byteenable for CSR to enable the byte enable for the CSR interface feature in the parameter editor of the Generic Serial Flash Interface Intel® FPGA IP.

The following steps are the programming flow using the CSR to write data to flash (Macronix* flash):
  1. Write the address that you intend to write data into. Write the address in the flash command address register (0x9). For example, write 0x2001.
  2. Write the writedata in the flash command write data 0 register (0xA) or flash command write data 1 register (0xB) using avl_csr_byteenable to select the desired bytes only. For example, the CSR byteenable of 4’b0110) for write data 0 is 44332211 and write data 1 is 88776655.
  3. Start the setup of the write operation opcode in the IP by writing to flash command setting register (0x7) with ‘write enable’ opcode (h06) and then set the control bit to 1 in flash control register (0x8).
  4. Next, write the write status register opcode (h01) in the same register (0x7). Set the data type as 'write' and write the number of data bytes as 8. For example, both write data 0 and write data 1 have 2 bytes enabled. You must write all the bytes (that is, 8 bytes) even if the intended total bytes to be written is 4.

    The resulting write operation writes 77663322 (4 bytes) into the flash address 0x2001.

Table 6.  Visualization of CSR byteenable for Write Data into Flash Memory
CSR Enabled Bytes in Write Data
CSR byteenable for write data 1 and 0 0 1 1 0
Write data 0 44 33 10 22 10 11
Write data 1 88 77 10 66 10 55
Write into Flash Memory
Flash address 0x2007 0x2006 0x2005 0x2004
Write data 1 FF 77 10 66 10 FF
Flash address 0x2003 0x2002 0x2001 0x2000
Write data 0 FF 33 10 22 10 FF
10 New data written into the flash.