Generic Serial Flash Interface Intel® FPGA IP User Guide

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ID 683419
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Generic Serial Flash Interface Intel® FPGA IP User Guide
1. Generic Serial Flash Interface Intel® FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Signals 1.4. Parameters 1.5. Register Map 1.6. Using Generic Serial Flash Interface Intel® FPGA IP 1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design 1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP 1.9. Intel HAL Driver 1.10. Generic Serial Flash Interface Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide
1.6. Using Generic Serial Flash Interface Intel® FPGA IP x
1.6.1. Control Status Register Byte Enable 1.6.2. Memory Operations 1.6.3. Byte Enabling 1.6.4. Constraining the I/O Pins
1.6.3. Byte Enabling x
1.6.3.1. Byte Enabling Supported Patterns
1.6.4. Constraining the I/O Pins x
1.6.4.1. General Purpose I/O 1.6.4.2. Dedicated Active Serial Interface
1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design x
1.7.1. Hardware and Software Requirements 1.7.2. Functional Description 1.7.3. Creating Nios® II Hardware System 1.7.4. Integrating Modules into Quartus® Prime Project 1.7.5. Programming the .sof File 1.7.6. Building Application Software System using Nios® II Software Build Tools
1.7.2. Functional Description x
1.7.2.1. Reference Design Components 1.7.2.2. Reference Design Application Program
1.7.6. Building Application Software System using Nios® II Software Build Tools x
1.7.6.1. Reference Design Results
1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP x
1.8.1. Flash Operations that Require Operation Code 1.8.2. Flash Operations to Read Flash Registers 1.8.3. Flash Operations to Write Flash Registers 1.8.4. Flash Operations that Require An Address 1.8.5. Read Memory from the Flash 1.8.6. Program Flash
1.9. Intel HAL Driver x
1.9.1. Driver API
1. Generic Serial Flash Interface Intel® FPGA IP User Guide

1.7.3. Creating Nios® II Hardware System

  1. In the Quartus® Prime software, go to File > New Project Wizard.
  2. Create a new Quartus® Prime Prime project named generic_flash_access in a new directory and select the Cyclone V E 5CEFA7F3117 device.
  3. Select Tools > Platform Designer, and save the file as generic_flash_access.qsys.
  4. Double-click on the clock source clk_0 and change the Clock frequency to 100000000 Hz (100MHz).
  5. Right click on clk_0 and rename it as sys_clk.
  6. Add a Nios® II processor:
    1. Go to Processor and Peripherals > Embedded Processors > Nios II Processor, and click Add.
    2. Click Finish to add the Nios® II processor to the design and rename it as nios2.
      Note: Ignore any messages about parameters that have not been specified yet.
  7. Add a Generic Serial Flash Interface IP:
    1. Select Basic Functions > Configuration and Programming > Generic Serial Flash Interface Intel FPGA IP, and click Add. Rename this component as intel_generic_serial_flash_interface_top0.
    2. Set the device density.
      Note: This reference design uses 1024MB flash device density.
    3. Connect data_master of processor to avl_mem and avl_csr, and instruction_master of processor to only avl_mem of this component.
  8. Add an On-chip Memory IP:
    1. Select Basic Functions > On Chip Memory > On-Chip Memory (RAM or ROM) Intel FPGA IP.
    2. Set the Total Memory Size to 40960 bytes (40 KBytes).
    3. Click Finish and rename as main_memory.
    4. Connect its slave to data_master and instruction_master of processor.
  9. Add a JTAG UART IP:
    1. Go to Interface Protocols > Serial > JTAG UART Intel FPGA IP, and click Add.
    2. Click Finish and rename it as jtag_uart.
    3. Connect its avalon_jtag_slave port to the data_master port of the processor.
    4. In the IRQ column, connect the interrupt sender port from the Avalon_jtag_slave port to the interrupt receiver port of the processor and type 0.
  10. Connect clock input of sys_clk to clock input of all other components.
  11. Resolve all Nios® II processor error messages before generating the Platform Designer system:
    1. Double click the Nios® II processor nios2.
    2. Click Vectors, change both the Reset vector memory and Exception vector memory to main_memory.s1.
    3. Click System tab and click on the drop-down menu System and click Assign Base Address to auto assign base addresses for all the components.
    4. Under the same menu, click Create Global Reset Network to connect the reset signals to form a global reset network.
    Figure 7. Completed Platform Designer Connection
  12. Generate the system:
    1. Click Generate HDL on the bottom of the window.
    2. When completed, the Platform Designer displays Generate: Completed successfully.
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