Generic Serial Flash Interface Intel® FPGA IP User Guide

ID 683419
Date 4/01/2024
Document Table of Contents

1.2. Device Family Support

The Generic Serial Flash Interface IP is supported in the following devices:

  • Agilex™ 5 2 3
  • Agilex™ 7 2 3 4
  • Stratix® 10 2 3
  • Arria® 10
  • Cyclone® 10 GX
  • Cyclone® 10 LP
  • MAX® 10 (For general purpose memory only) 2
  • Stratix® V
  • Arria® V
  • Cyclone® V
  • Stratix® IV
  • Cyclone® IV
  • Arria® II
2 Export the flash pin by enabling the Enable SPI pins interface parameter of this IP.
3 The IP can only access flash that is connected to FPGA GPIO pins. You cannot use the IP to access flash that is connected to SDM for configuration purpose.
4 For Agilex™ 7 F-Series and I-Series devices, do not place the exported conduit pins in the same x4 DQ group because they have different Output Enable (OE) signals. OE conflict during compilation can trigger Error(175005). Refer to the Agilex™ 7 General Purpose I/O User Guide: F-Series and I-Series and the KDB Answer Error (175005): Could not find a location with: GPIO_SHARED_NOE0 of (locations affected) for more information.