Generic Serial Flash Interface Intel® FPGA IP User Guide

ID 683419
Date 11/09/2021
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1.6. Using Generic Serial Flash Interface Intel® FPGA IP

The Generic Serial Flash Interface Intel® FPGA IP core interfaces are Avalon® memory-mapped compliant. For more details, refer to the Avalon® specification.
Note:
  • For operations that require write value to flash, you must perform write enable operation first.
  • You must read the flag status register every time you issue a write or erase command.
  • In case of support multiples flash devices, you must write chip select register to select the correct flash device before performing any operation to the specific flash device.