1. Generic Serial Flash Interface Intel® FPGA IP User Guide
|Intel® Quartus® Prime Design Suite 21.2|
|IP Version 20.1.1|
You can use the Generic Serial Flash Interface Intel® FPGA IP to write the following data to the flash device:
- Configuration memory 1—configuration data for Active Serial (AS) configuration scheme.
- General purpose memory— application-specific data.
The Generic Serial Flash Interface IP supports the following features:
- Single, dual or quad I/O mode.
- Direct flash access via the Avalon® memory-mapped slave interface which allows a processor such as Nios® II to directly execute codes from the flash.
- Up to 3 flash device support ( Intel® Arria® 10 devices, Intel® Cyclone® 10 GX devices, and other FPGA devices with flashes that are connected to the FPGA GPIO pins).
- IP control register for accessing flash control and status registers.
- Programmable clock generator with run-time baud rate change for flash device clock.
- Programmable chip select delay.
- Read data capturing logic when running with high frequency.
- FPGA active serial memory interface (ASMI) block atom connection to the active serial (AS) pins or export to FPGA I/O pins.
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