Generic Serial Flash Interface Intel® FPGA IP User Guide

ID 683419
Date 11/09/2021
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1.3. Signals

Figure 1. Signal Block DiagramThe inclusion and width of some signals depend on the features selected.
Table 2.  Ports Description
Signal Width Direction Description
Avalon® Memory-Mapped Slave Interface for CSR (avl_csr)
avl_csr_addr 6 Input Avalon® memory-mapped address bus. The address bus is in word addressing.
avl_csr_read 1 Input Avalon® memory-mapped read control to the CSR.
avl_csr_rddata 32 Output Avalon® memory-mapped read data bus from the CSR.
avl_csr_write 1 Input Avalon® memory-mapped write control to the CSR.
avl_csr_wrdata 32 Input Avalon® memory-mapped write data bus to CSR.
avl_csr_waitrequest 1 Output Avalon® memory-mapped waitrequest control from the CSR.
avl_csr_rddata_valid 1 Output Avalon® memory-mapped read data valid that indicates the CSR read data is available.
avl_csr_byteenable 4 Input Avalon® memory-mapped byteenable control to the CSR. Available when you enable the Use byteenable for CSR parameter.
Avalon® Memory-Mapped Slave Interface for Memory Access (avl_mem)
avl_mem_write 1 Input Avalon® memory-mapped write control to the memory
avl_mem_burstcount 7 Input Avalon® memory-mapped burst count for the memory. The value range from 1 to 64 (Max page size).
avl_mem_waitrequest 1 Output Avalon® memory-mapped waitrequest control from the memory.
avl_mem_read 1 Input Avalon® memory-mapped read control to the memory
avl_mem_addr N Input

Avalon® memory-mapped address bus. The address bus is in word addressing. The width of the address depends on the flash memory density.

If you are using Intel® Arria® 10, and Intel® Cyclone® 10 GX or any supported devices with general purpose I/O with multiples flashes, write the CSR to select the chip select. The IP targets the selected flash when being accessed via this address.
avl_mem_wrdata 32 Input Avalon® memory-mapped write data bus to the memory
avl_mem_readddata 32 Output Avalon® memory-mapped read data bus from the memory.
avl_mem_rddata_valid 1 Output Avalon® memory-mapped read data valid that indicates the memory read data is available.
avl_mem_byteenble 4 Input Avalon® memory-mapped write data enable bus to memory. During bursting mode, byteenable bus will be logic high, 4’b1111.
Clock and Reset
clk 1 Input Input clock to clock the IP.
reset 1 Input Asynchronous reset to reset the IP.
Interrupt
Irq 1 Output Interrupt signal that indicate if there is an illegal write or illegal erase.
Conduit Interface 5
flash_data 4 Bidirectional Input or output port to feed data from the flash device.
flash_dclk 1 Output Provides clock signal to the flash device.
flash_ncs 1/3 Output Provides the ncs signal to the flash device.
5 Available when you enable the Enable SPI pins interface parameter.