Generic Serial Flash Interface Intel® FPGA IP User Guide

ID 683419
Date 11/09/2021

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Document Table of Contents

1.4. Parameters

Table 3.  Parameter Settings
Parameter Legal Values Descriptions
Device Density 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048 Density of the flash device used in Mb.
Disable dedicated Active Serial interface Routes the signals to the top level of your design. Enable this when you want to include the Serial Flash Loader Intel FPGA IP in your design.
Enable SPI pins interface Translates the signals to the SPI pin interface.
Number of Chip Select used




Selects the number of chip select connected to the flash.
Enable flash simulation model Uses the default EPCQ1024 simulation model for simulation. When disabled, refer to AN-720: Simulating the ASMI Block in Your Design for creating a wrapper to use with other flash simulation model.
Use byteenable for CSR Turns on byteenable for CSR writedata interface.