Generic Serial Flash Interface Intel® FPGA IP User Guide

ID 683419
Date 11/09/2021
Public
Download

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.11.09 21.2 20.1.1 Updated CS Delay Setting Register in Register Map topic.
2021.06.21 21.2 20.1.1
  • Updated Device Family Support.
  • Updated Nios® II HAL Driver:
    • Updated the intel_gsfi_get_info description in Table: intel_gsfi_get_info.
    • Updated the intel_gsfi_read description in Table: intel_gsfi_read.
    • Nios® II HAL Driver
  • Removed the Driver API Application topic.
  • Updated Figure: Reference Design Block Diagram.
2021.03.29 21.1 20.1.1
  • Added the following sections:
    • Nios II HAL Drivers
    • Driver API
    • Driver API Application
  • Corrected the default value for dummy cycles from 0xA to 0x0 in Table: Register Map.
  • Updated the steps in the Perform Page Program (Extended Mode) and Perform 4-byte Quad Input Fast Program (Quad SPI Mode) examples in Program Flash.
2020.09.28 20.3 20.0.0
  • Added a new register setting—tSHSL.
  • Added a new section—Constraining the I/O Pins.
  • Updated the description for Enable flash simulation model in Table: Parameter Settings.
  • Removed Control Status Register Operations.
  • Updated the following topics:
    • Generic Serial Flash Interface Intel® FPGA IP User Guide
    • Release Information
    • Memory Operations
  • Updated the Hardware and Software Requirements of the Generic Serial Flash Interface Intel® FPGA IP Reference Design section.
  • Updated the description of On-Chip Memory Intel® FPGA IP in Table: Reference Design Components Descriptions.
  • Updated Creating Nios® II Hardware System:
    • Updated the description in step 7c.
    • Updated Figure: Completed Platform Designer Connection.
  • Made minor editorial updates through out the document.
2020.05.08 20.1 19.2.1
  • Added new sections—Release Information and Control Status Register Byte Enable.
  • Updated Table: Parameter Settings to include a new parameter—Use byteenable for CSR.
  • Added a new signal—avl_csr_byteenable.
  • Updated Figure: Signal Block Diagram.
  • Updated the note to the Device Family Support topic.
2020.04.13 19.4 19.1.1
  • Renamed document title as Generic Serial Flash Interface Intel® FPGA IP User Guide
  • Added the Byte Enabling section.
  • Added a note to the Device Family Support topic.
  • Updated the Memory Operations topic.
  • Updated for latest branding standards.
2019.11.27 19.3 19.1 Added a note to the Memory Operations topic.
2019.09.30 19.3 19.1
  • Added support for Intel® Agilex™ devices.
  • Updated the Device Family Support topic.
  • Made minor editorial updates to the document.
2018.11.09 18.1 18.1
  • Added the Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP Core section.
  • Added the Generic Serial Flash Interface Intel® FPGA IP Core User Guide Archives section.
  • Updated the Generic Serial Flash Interface Intel® FPGA IP Core User Guide section to provide more information on the Generic Serial Flash Interface Intel® FPGA IP core.
  • Updated the signal names of the Signal Block Diagram figure.
  • Updated the Conduit Interface signal names in the Ports Description table.
  • Updated the description of the write opcode field name of the write instruction register in the Register Map table.
2018.05.16 18.0 18.0
  • Updated the Generic Serial Flash Interface Intel FPGA IP Core Reference Design Files link.
  • Added Flash Command Address Register in the Register Map.
2018.05.07 18.0 18.0 Initial release.