Generic Serial Flash Interface Intel® FPGA IP User Guide

ID 683419
Date 11/09/2021
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1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP

This section provides information on how to use the registers of this IP to perform flash access. To begin, build the Platform Designer system with a few components (clock, jtag master, pll, and this IP) as shown below. Then, use the flash operations in the next example.

Figure 8. Example of Creating Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP
Note: You must set the MSEL pins of the FPGA devices to the AS configuration mode. For Intel® MAX® 10 devices, you must enable the Enable SPI Pins Interface parameter of this IP.

Flash operations are divided into several categories. Example of operations, registers to use, and sample .tcl scripts for each category are provided.