F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 7/14/2022
Public

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3.3. Simulating the Design Example

Generating tile files

The tile files are generated during the design example generation. Runnning Support-Logic Generation manually is not required before simulating the design example.

Tile files generation is a required step before simulation if you created your design with the F-Tile Avalon-ST IP for PCI Express from scratch. You can run Analysis & Elaboration on the Processing menu in the Intel® Quartus® Prime Pro Edition software to generate the F-Tile specific tiles file for your design. The Support-Logic Generation command runs automatically as part of the process.

A successful tile file generation results in the <IP_instance_name>__tiles.x files where x represents the necessary file extensions. The generated files are located in your project directory and contain the full netlist for simulation and synthesis.

Figure 20. Procedure
  1. Run the simulation script under <example_design>/pcie_ed_tb/pcie_ed_tb/sim/<simulator> directory for the simulator of your choice. Refer to the table below.
  2. Analyze the results.
Note: F-Tile does not support parallel PIPE simulations.
Table 3.  Steps to Run Simulation
Simulator Working Directory Instructions

VCS*

<example_design>/pcie_ed_tb/pcie_ed_tb/sim/synopsys/vcs/
  1. Run the following commands:

    For FASTSIM mode:
    sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS="+vcs+lic+wait\ -full64\ -hsopt=gates\ -debug_pp\ +define+RTLSIM\ +define+IP7581SERDES_UX_SIMSPEED\ +define+SSM_SEQUENCE\ +notimingcheck\ +nospecify\ " |tee simulation.log
    For non-FASTSIM mode:
    sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="+vcs+lic+wait\ -full64\ -hsopt=gates\ -debug_pp\ +define+RTLSIM\ +define+SSM_SEQUENCE\" USER_DEFINED_SIM_OPTIONS="" | tee simulation.log
    Note: The commands above are single-line commands.
  2. A successful simulation ends with the following message,
    "Simulation stopped due to successful completion!"
    in the simulation.log file that was generated.
Note: To run a simulation in interactive mode, use the following steps: (if you already generated a simv executable in noninteractive mode, delete the simv and simv.diadir)
  1. Open the vcs_setup.sh file and add a debug option to the VCS command:
    vcs -debug_access+all
  2. Compile the design example:

    For FASTSIM mode:
    sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS="+vcs+lic+wait\ -full64\ -hsopt=gates\ -debug_pp\ +define+RTLSIM\ +define+IP7581SERDES_UX_SIMSPEED\ +define+SSM_SEQUENCE\ " SKIP_SIM=1
    For non-FASTSIM mode:
    sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS="+vcs+lic+wait\ -full64\ -hsopt=gates\ -debug_pp\ +define+RTLSIM\ +define+SSM_SEQUENCE\ " SKIP_SIM=1
    Note: The commands above are single-line commands.
  3. Start the simulation in interactive mode:
    simv -gui &

VCS* MX

<example_design>/pcie_ed_tb/pcie_ed_tb/sim/synopsys/vcsmx/
  1. Run the following commands:
    For FASTSIM mode:
    sh vcsmx_setup.sh USER_DEFINED_COMPILE_OPTIONS="+define+RTLSIM\ +define+IP7581SERDES_UX_SIMSPEED\ +define+SSM_SEQUENCE\ -sverilog\ +define+QUARTUS_ENABLE_DPI_FORCE\ " USER_DEFINED_ELAB_OPTIONS="\$QUARTUS_INSTALL_DIR/eda/sim_lib/quartus_dpi.c\ -debug_access+f\ +vcs+lic+wait\ -full64\ -hsopt=gates\ -debug_pp\ " USER_DEFINED_SIM_OPTIONS="" | tee simulation.log
    For non-FASTSIM mode:
    sh vcsmx_setup.sh USER_DEFINED_COMPILE_OPTIONS="+define+RTLSIM\ +define+SSM_SEQUENCE\ -sverilog\ +define+QUARTUS_ENABLE_DPI_FORCE\ " USER_DEFINED_ELAB_OPTIONS="\$QUARTUS_INSTALL_DIR/eda/sim_lib/quartus_dpi.c\ -debug_access+f\ +vcs+lic+wait\ -full64\ -hsopt=gates\ -debug_pp\ " USER_DEFINED_SIM_OPTIONS="" | tee simulation.log
    Note: The commands above are single-line commands.
  2. A successful simulation ends with the following message,
    "Simulation stopped due to successful completion!"
    in the simulation.log file that was generated.
Note: To run a simulation in interactive mode, use the following steps: (if you already generated a simv executable in noninteractive mode, delete the simv and simv.diadir)
  1. Open the vcsmx_setup.sh file and add a debug option to the VCS command:
    vcs -debug_access+all
  2. Compile the design example:

    For FASTSIM mode:
    sh vcsmx_setup.sh USER_DEFINED_COMPILE_OPTIONS="+define+RTLSIM\ +define+IP7581SERDES_UX_SIMSPEED\ +define+SSM_SEQUENCE\ -sverilog\ " USER_DEFINED_ELAB_OPTIONS="+vcs+lic+wait\ -full64\ -hsopt=gates\ -debug_pp\ " USER_DEFINED_SIM_OPTIONS="" SKIP_SIM=1
    For non-FASTSIM mode:
    sh vcsmx_setup.sh USER_DEFINED_COMPILE_OPTIONS="+define+RTLSIM\ +define+SSM_SEQUENCE\ -sverilog\ " USER_DEFINED_ELAB_OPTIONS="+vcs+lic+wait\ -full64\ -hsopt=gates\ -debug_pp\ " USER_DEFINED_SIM_OPTIONS="" SKIP_SIM=1
    Note: The commands above are single-line commands.
  3. Start the simulation in interactive mode:
    simv -gui &

QuestaSim*

ModelSim* - Intel® FPGA Starter Edition

Questa* Intel® FPGA Starter Edition

<example_design>/ pcie_ed_tb/pcie_ed_tb/sim/mentor/

  1. Invoke vsim (by typing vsim, which brings up a console window where you can run the following commands).
  2. do msim_setup.tcl
  3. set TOP_LEVEL_NAME "pcie_ed_tb.pcie_ed_tb" [required for Windows environment only]
  4. set USER_DEFINED_COMPILE_OPTIONS "+define+IP7581SERDES_UX_SIMSPEED" [to enable FASTSIM mode]
  5. ld_debug
  6. run -all
  7. A successful simulation ends with the following message:
    "Simulation stopped due to successful completion!"

Xcelium*

<example_design>/ pcie_ed_tb/pcie_ed_tb/sim/xcelium/

  1. Run the following commands:

    For FASTSIM mode:
    sh xcelium_setup.sh USER_DEFINED_VERILOG_COMPILE_OPTIONS="+define+RTLSIM\ +define+IP7581SERDES_UX_SIMSPEED\ +define+SSM_SEQUENCE\ -sv\" USER_DEFINED_ELAB_OPTIONS="-timescale\ 1ns/1ps" USER_DEFINED_SIM_OPTIONS="-input\ @run" | tee simulation.log
    For non-FASTSIM mode:
    sh xcelium_setup.sh USER_DEFINED_VERILOG_COMPILE_OPTIONS="+define+RTLSIM\ +define+SSM_SEQUENCE\ -sv\" USER_DEFINED_ELAB_OPTIONS="-timescale\ 1ns/1ps" USER_DEFINED_SIM_OPTIONS="-input\ @run" | tee simulation.log
    Note: The commands above are single-line commands.
  2. A successful simulation ends with the following message in the simulation.log file that was generated.
    "Simulation stopped due to successful completion!"

The simulation reports, "Simulation stopped due to successful completion" if no errors occur.

The same procedure applicable for PCIe Gen3/4 x16, PCIe Gen3/4 x8x8 and PCIe Gen3/4 x8 design example variants.