F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 7/14/2022
Public

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2.2. Single Root I/O Virtualization (SR-IOV) Design Example

Figure 10. PCIe Gen 4 x16 Single Root I/O Virtualization (SR-IOV) Design Example Block Diagram

The SR-IOV design example performs memory transfers from a host processor to a target Intel Agilex device configured as Gen4 x16 Endpoint. The design example runs up to 500 MHz at user interface with the maximum data width interface of 512 bits. It demonstrates the SR-IOV capability of 2 PF and up to 32 VF per PF. With two PFs and 32 VFs per PF, there are 66 memory locations that the design example can access. The two PFs can access two memory locations, while the 64 VFs (2 x 32) can access 64 memory locations.

The design example is intended to handle simple read/write instructions based on TLP command. TLP transaction of memory write request (MWr) writes the data to the designated RAM memory space. As for the TLP transaction of memory read request (MRd), the design reads the data from RAM memory space and returns completion with data (CplD). The data and address requested to access the SR-IOV APPS must be double word aligned.

The SR-IOV design example automatically creates the files necessary to simulate and compile in the Intel® Quartus® Prime software. The design example covers a wide range of parameters. However, it does not cover all possible parameterizations of the F-Tile Hard IP for PCIe.

This design example consists of 2 main components:
  • F-Tile Avalon-ST IP for PCI Express Hard IP Endpoint variant (DUT)
  • The SR-IOV Application (APPS)