SDI II Intel® Stratix 10 FPGA IP Design Example User Guide

ID 683368
Date 3/28/2022

A newer version of this document is available. Customers should click here to go to the newest version.

2.9. Upgrading Your Design

When you upgrade your designs to a later version, you may have to add, remove, or edit some of the generated files.

Upgrading from Previous Versions of the Intel® Quartus® Prime Pro Edition Software

  1. Click IP Upgrade to upgrade all the IP and Platform Designer files.
  2. If you have triple-rate or multi-rate designs, update all the Native PHY config files location to the latest version in the simulation run script. For example, in the file, update the version as in the following line:
    vlog -sv \$USER_DEFINED_VERILOG_COMPILE_OPTIONS  "\$QSYS_SIMDIR/../rtl/du/sdi_rx_phy/altera_xcvr_native_a10_<version>/
    Note: You should be able to find the updated Native PHY library path in the specified folder indicated in the line.
  3. Generate the same design example configuration in the new Intel® Quartus® Prime release version.
  4. Compare the whole design example directory; replace the files that have changes with the new files and copy over the new files to your existing design.

Did you find the information on this page useful?

Characters remaining:

Feedback Message