SDI II Intel® Stratix 10 FPGA IP Design Example User Guide

ID 683368
Date 3/28/2022

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1.5.2. Design Considerations

You need to consider certain issues when instantiating the SDI II Intel® FPGA IP design examples.

  • Serial loopback designs:
    • The serial loopback design is mainly for image and TX clock switching demonstrations only. To get a more accurate jitter performance with the daughter card components, use the parallel loopback design and connect it to a clean video source.
    • To allow segmented frame video format (1080sF30, 1080sF25) and interlaced video format (1080i60, 1080i50) to be correctly differentiated in the external analyzer, Payload ID must be inserted in the serial loopback design.
    • The Omnitek Ultra 4K Analyzer (software version 2.1) may not detect 12G-SDI 2160p59.94 in the serial loopback design. If you encounter such problem, upgrade the Omnitek Ultra 4K analyzer to a later version.