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1.4. Simulating the Design
The SDI II Intel® FPGA IP design example testbench simulates one channel serial loopback design with TX instance connected to an internal video pattern generator. The serial output from the TX instance connects to the RX instance in the testbench. The testbench also includes checkers and control mechanisms.
Figure 4. Design Simulation Flow
- Navigate to the simulation folder of your choice.
- Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator.
- Analyze the results.
Table 3. Steps to Run Simulation Simulator Working Directory Instructions Riviera-PRO* /simulation/aldecIn the GUI, type:
Xcelium* /simulation/xceliumIn the command line, type:
ModelSim* /simulation/mentorIn the GUI, type:
VCS* /simulation/synopsys/vcsIn the command line, type:
VCS* MX /simulation/synopsys/vcsmxIn the command line, type:
source vcsmx_sim.shA successful simulation ends with the following message:
#### TRANSMIT TEST COMPLETED SUCCESSFULLY! #### # #### Channel 1: RECEIVE TEST COMPLETED SUCCESSFULLY! ####
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