SDI II Intel® Stratix 10 FPGA IP Design Example User Guide

ID 683368
Date 3/28/2022

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2.1. Parallel Loopback Design Examples

Note: For parallel loopback designs, do not share the TX PLL reference clock with the RX transceiver reference clock. The design logic tunes the TX PLL clock to match the RX recovered clock frequency. For the parallel loopback with external VCXO designs (single-rate and triple-rate), use the only 148.5 MHz on-board oscillator as the TX PLL reference clock. For the RX reference clock, use a 148.5 MHz clock from another on-board oscillator.
Figure 8. Parallel Loopback with Simplex Mode Block Diagram
Figure 9. Parallel Loopback with Simplex Mode Clocking Scheme
Figure 10. Parallel Loopback with Duplex Mode Block Diagram
Figure 11. Parallel Loopback with Duplex Mode Clocking Scheme