SDI II Intel® Stratix 10 FPGA IP Design Example User Guide

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ID 683368
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Design Example Quick Start Guide 2. SDI II Intel® FPGA IP Design Example Detailed Description 3. SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for the SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide
1. SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel® FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines Connections and Settings for HD/3G-SDI Single Rate and Triple Rate Designs Connections and Settings for Multi Rate Design 1.5.2. Design Considerations
2. SDI II Intel® FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. SDI II Intel® FPGA IP Design Example Quick Start Guide
2. SDI II Intel® FPGA IP Design Example Detailed Description
3. SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for the SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide

1.5.1. Connection and Settings Guidelines

Before programing with the .sof file, ensure that the connections and settings are correct.

Connections and Settings for HD/3G-SDI Single Rate and Triple Rate Designs

  • For parallel loopback design, the on-board HD-BNC RX connector (J18) connects to an external video source and the on-board HD-BNC TX connector (J17) connects to a video analyzer.
  • For serial loopback design, the on-board HD-BNC TX connector (J17) connects to an on-board HD-BNC RX connector (J18) or a video analyzer.
  • Ensure all switches on the development board are in default position.
    Note: Make sure to set both SW1.1 and SW1.2 to 1 to enable JTAG Only Mode.
  • The SDI video analyzer displays the video generated from the source.
    Note: For parallel loopback designs, you may need to switch the Si516_FS (SW4.2) at the back of the board if you are switching between fractional frame rate and integer frame rate video format.
Table 4.  SW1 DIP Switch Default Settings (Top of the Board)
Switch Board Label Description
1 MSEL2
  • MSEL2, MSEL1 = [0,0] QSPI AS Fast Mode
  • MSEL2, MSEL1 = [0,1] QSPI AS Normal Mode
  • MSEL2, MSEL1 = [1,0] AVST x16 Mode (Default)
  • MSEL2, MSEL1 = [1,1] JTAG Only Mode
2 MSEL1
Table 5.  SW4 DIP Switch Default Settings (Bottom of the Board)
Switch Board Label Description
1 RZQ_B2M
  • ON for setting the RZQ resistor of Bank 2M to 99.17 ohm
  • OFF for setting the RZQ resistor of Bank 2M to 240 ohm (Default position)
2 SI516_FS
  • ON for setting SDI REFCLK frequency to 148.35 MHz
  • OFF for setting SDI REFCLK frequency to 148.5 MHz (Default position)
Table 6.  SW6 DIP Switch Default Settings (Bottom of the Board)
Switch Board Label Description
1 Stratix 10
  • ON to bypass Intel® Stratix® 10 in the JTAG chain
  • OFF to enable Intel® Stratix® 10 in the JTAG chain (Default position)
2 MAX V
  • ON to bypass MAX® V in the JTAG chain
  • OFF to enable MAX® V in the JTAG chain (Default position)
3 FMC
  • ON to bypass the FMC connector in the JTAG chain (Default position)
  • OFF to enable the FMC connector in the JTAG chain

Connections and Settings for Multi Rate Design

  • A VIDIO™ FMC Development Module VIDIO-12G-A (Nextera 12G SDI FMC) daughter card or Terasic 12G-SDI FMC daughter card connects to the FMC Port A on the development board.
  • For parallel loopback design, the BNC RX connector connects to an external video source and the TX connector connects to a video analyzer.
  • For serial loopback design, the BNC TX connector connects to the BNC RX connector or a video analyzer.
Table 7.  BNC RX and TX Connector Ports
FMC Daughter Card BNC RX Connector Port BNC TX Connector Port
Nextera 12G SDI FMC daughter card J2/12G In J1/12G Out
Terasic 12G-SDI FMC daughter card 12G-SDI In 0 12G-SDI Out 0
  • Ensure all switches on the development board are in default position.
    Note: Make sure that to set both SW1.1 and SW1.2 to 1 to enable JTAG Only Mode, and turn off SW6.3 to enable the FMC connector.
  • The SDI video analyzer displays the video generated from the source.

Note: For Nextera 12G SDI FMC daughter card, change the jumper (J8) position before switching between fractional frame rate and integer frame rate video formats. Press the push button (PB0) to trigger a device (LMK03328) power cycling through the PDN pin every time you change the jumper (J8) position.
Figure 6. Jumper Settings on Nextera 12G-SDI FMC Daughter CardRefer to these settings to change the jumper (J8) position.
Table 8.  Jumper Settings Description
Jumper Block Description
J7 Programming header
J8 To switch the generated clock frequency for the TX channel:
  • Pin 1–2 = 297 MHz
  • Pin 2–3 = 297/1.001 MHz
J9 To select SDI or IP mode:
  • Pin 1–2 = SDI mode
  • Pin 2–3 = IP mode
Related Information
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