SDI II Intel® Stratix 10 FPGA IP Design Example User Guide

ID 683368
Date 3/28/2022
Public

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1.5. Compiling and Testing the Design

To compile and run a demonstration test on the hardware design example, follow these steps:
  1. Ensure that the hardware design example generation is complete.
  2. Open quartus/sdi_ii_s10_demo.qpf.
  3. Click Processing > Start Compilation.
  4. After successful compilation, the Intel® Quartus® Prime Pro Edition software generates a .sof file in your specified directory.
    Note: The compilation must complete before you power up the board and make the necessary clock controller settings. After powering up the board, you must perform the following steps 5 and 6 within 18 seconds.
  5. Open the Clock Controller parameter editor, and set the clock frequency in the Si5341 tab.
    • HD/3G-SDI single-rate and triple-rate designs:
      • For parallel loopback with external VCXO designs, set Out1 frequency to 148.5 MHz.
      • For parallel loopback without external VCXO designs, set Out1 frequency to 100 MHz.
      • If you turn on the Dynamic Tx clock switching parameter in the Design Example parameter editor, set Out1 frequency to 148.35165 MHz.
    • Multi-rate designs:
      • For parallel loopback with external VCXO designs, set Out1 frequency to 148.5 MHz.
      • For parallel loopback without external VCXO designs, set Out4 frequency to 148.5 MHz, and set Out5 frequency to 245 MHz.
      • If you turn on the Dynamic Tx clock switching parameter in the Design Example parameter editor, set Out4 frequency to 148.3516 MHz, and set Out5 frequency to 148.5 MHz.
    Figure 5. Clock Controller - Si5341
  6. Configure the selected device on the development board using the generated .sof file (Tools > Programmer ).
    Note: If you missed setting the clock controller and program the device within 18 seconds, you will get an error message. In this case, power cycle the development board and program the .sof file first. Then, specify the settings for the clock controller and program the .sof file again.
  7. For serial loopback designs, open the System Console to control the internal video pattern generator. Click Tools > System Debugging Tools > System Console.
    Note: Close the Clock Controller GUI and the Programmer window before you open the System Console.
  8. After the initialization, type source ../hwtest/tpg_ctrl.tcl in the System Console to open the pattern generator control user interface. Select your desired video format.