SDI II Intel® Stratix 10 FPGA IP Design Example User Guide

ID 683368
Date 3/28/2022

A newer version of this document is available. Customers should click here to go to the newest version.

2. SDI II Intel® FPGA IP Design Example Detailed Description

The SDI II Intel® FPGA IP core includes these design examples for Intel® Stratix® 10 devices.
  • Parallel loopback with external VCXO
  • Parallel loopback without external VCXO
  • Serial loopback


  • All designs use LED status for early debugging stage.
  • The simplex serial loopback designs include RX and TX options. To use RX or TX only components, remove the irrelevant blocks from the designs.
    User Requirement Preserve Remove
    RX Only RX Top
    • TX Top
    TX Only TX Top
    • RX Top
Figure 7. Components Required for Intel® Stratix® 10 TX or RX Only Design